Jeroen Dobbelaere <jeroen.dobbelaere@acunia.com>

Jeroen Dobbelaere  <jeroen.dobbelaere@acunia.com>
* config/arm/arm.md (sign_extract_onebit, not_signextract_onebit):
Add clobber of the condition code register.

From-SVN: r57348

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eda02218a36e7c7c7841a408f580e3272261907a..0b9583504323b710f83e3d4afc84e9253dc93e29 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2002-09-20  Jeroen Dobbelaere  <jeroen.dobbelaere@acunia.com>
+
+       * config/arm/arm.md (sign_extract_onebit, not_signextract_onebit):
+       Add clobber of the condition code register.
+
 2002-09-18  Richard Earnshaw (rearnsha@arm.com)
 
        PR optimization/7967

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index e4de911de0e93c8226055c7543caca96c963e292..5180c75933a2efd3cd2c9cac84b2dff646f38b06 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -8948,7 +8948,8 @@
   [(set (match_operand:SI 0 "s_register_operand" "=r")
        (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
                         (const_int 1)
-                        (match_operand:SI 2 "const_int_operand" "n")))]
+                        (match_operand:SI 2 "const_int_operand" "n")))
+    (clobber (reg:CC CC_REGNUM))]
   "TARGET_ARM"
   "*
     operands[2] = GEN_INT (1 << INTVAL (operands[2]));
@@ -8964,7 +8965,8 @@
        (not:SI
         (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
                          (const_int 1)
-                         (match_operand:SI 2 "const_int_operand" "n"))))]
+                         (match_operand:SI 2 "const_int_operand" "n"))))
+   (clobber (reg:CC CC_REGNUM))]
   "TARGET_ARM"
   "*
     operands[2] = GEN_INT (1 << INTVAL (operands[2]));