]> git.ipfire.org Git - thirdparty/openwrt.git/commitdiff
realtek: dsa: rtl838x: drop redundant SMI_GLB_CTRL accesses 21868/head
authorBjørn Mork <bjorn@mork.no>
Wed, 4 Feb 2026 15:02:08 +0000 (16:02 +0100)
committerRobert Marko <robimarko@gmail.com>
Thu, 5 Feb 2026 10:38:13 +0000 (11:38 +0100)
Bit 15 of the rtl838x SMI_GLB_CTRL register is set early during mdio reset
and never cleared.  There is no need to set it again.

Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/21868
Signed-off-by: Robert Marko <robimarko@gmail.com>
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c

index a24009ecd6c12756311f4f1ca0c3049217c7d448..8ed55f55d797230b5df593c403e153f66a37c316 100644 (file)
@@ -366,14 +366,9 @@ static int rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
        /* Disable MAC polling the PHY so that we can start configuration */
        priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
 
-       /* Enable PHY control via SoC */
-       if (priv->family_id == RTL8380_FAMILY_ID) {
-               /* Enable PHY control by telling SoC that "PHY patching is done" */
-               sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
-       } else if (priv->family_id == RTL8390_FAMILY_ID) {
-               /* Disable PHY polling via SoC */
+       /* Disable PHY polling via SoC */
+       if (priv->family_id == RTL8390_FAMILY_ID)
                sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
-       }
 
        return 0;
 }
index 29052ff1b9194f2038e4c05a3e97202d04d42f9e..d33e0fa449ecca02ab0937e35fa7aebd91c54ee4 100644 (file)
@@ -60,8 +60,6 @@ static void rtldsa_enable_phy_polling(struct rtl838x_switch_priv *priv)
        /* PHY update complete, there is no global PHY polling enable bit on the 93xx */
        if (priv->family_id == RTL8390_FAMILY_ID)
                sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
-       else if (priv->family_id == RTL8380_FAMILY_ID)
-               sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
 }
 
 const struct rtldsa_mib_list_item rtldsa_838x_mib_list[] = {