]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
clk: renesas: rzv2h: Re-assert reset on deassert timeout
authorTommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Wed, 3 Sep 2025 08:27:52 +0000 (10:27 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 13 Nov 2025 20:37:36 +0000 (15:37 -0500)
[ Upstream commit f8c002165ca27d95d3d15e865dd0a47c0a1b14dd ]

Prevent issues during reset deassertion by re-asserting the reset if a
timeout occurs when trying to deassert. This ensures the reset line is in a
known state and improves reliability for hardware that may not immediately
clear the reset monitor bit.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/20250903082757.115778-4-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/renesas/rzv2h-cpg.c

index f468afbb54e2d192c094e0048a698664ae99bd00..5dfe660d13422679af2878cd670e3ab257d47e9e 100644 (file)
@@ -864,6 +864,7 @@ static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
        u32 mask = BIT(priv->resets[id].reset_bit);
        u8 monbit = priv->resets[id].mon_bit;
        u32 value = mask << 16;
+       int ret;
 
        dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
                assert ? "assert" : "deassert", id, reg);
@@ -875,9 +876,15 @@ static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
        reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
        mask = BIT(monbit);
 
-       return readl_poll_timeout_atomic(priv->base + reg, value,
-                                        assert ? (value & mask) : !(value & mask),
-                                        10, 200);
+       ret = readl_poll_timeout_atomic(priv->base + reg, value,
+                                       assert ? (value & mask) : !(value & mask),
+                                       10, 200);
+       if (ret && !assert) {
+               value = mask << 16;
+               writel(value, priv->base + GET_RST_OFFSET(priv->resets[id].reset_index));
+       }
+
+       return ret;
 }
 
 static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,