arm64: dts: imx8mm-var-som-symphony: Enable I2C4

Enable I2C4 on the Symphony carrier and add pinctrl configuration,
including GPIO-based bus recovery support.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
index 6112e4392c5957d8b3a9c79af0c084ecbb091f28..fbad5d2d4a97adc5f15344e53f4f0353f4cdaa1b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
@@ -188,6 +188,16 @@
        };
 };
 
+&i2c4 {
+       clock-frequency = <100000>;
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c4>;
+       pinctrl-1 = <&pinctrl_i2c4_gpio>;
+       scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       status = "okay";
+};
+
 /* Header */
 &uart1 {
        pinctrl-names = "default";
@@ -281,6 +291,20 @@
                >;
        };
 
+       pinctrl_i2c4: i2c4grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c3
+                       MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c3
+               >;
+       };
+
+       pinctrl_i2c4_gpio: i2c4gpiogrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20        0x1c3
+                       MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21        0x1c3
+               >;
+       };
+
        pinctrl_pca9534: pca9534grp {
                fsl,pins = <
                        MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x16