mtd: spi-nor: winbond: Add W25Q02NWxxIM CMP locking support

This chip has support for the locking complement (CMP) feature. Add
the relevant bit to enable it.

Unfortunately, this chip also comes with an incorrect BFPT table,
indicating the Control Register cannot be read back. This is wrong,
reading back the register works and has no (observed) side effect. The
datasheet clearly indicates supporting the 35h command and all bits from
the CR are marked readable. QE and CMP bits are inside, and can be
properly read back.

Add a fixup for this, otherwise it would defeat the use of the CMP
feature.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>

diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 3a3b7f2f16598ae03a2fb59e2a90769a8b778b11..8ebdbcec0b3fdec88dbd46f0eee03119e7f341d8 100644 (file)
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -379,7 +379,9 @@ static const struct flash_info winbond_nor_parts[] = {
        }, {
                /* W25Q02NWxxIM */
                .id = SNOR_ID(0xef, 0x80, 0x22),
-               .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP,
+               .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
+                        SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
+               .fixups = &winbond_rdcr_fixup,
        }, {
                /* W25H512NWxxAM */
                .id = SNOR_ID(0xef, 0xa0, 0x20),