static inline void aie2_tdr_signal(struct amdxdna_dev *xdna)
{
- WRITE_ONCE(xdna->dev_handle->tdr_status, AIE2_TDR_SIGNALED);
+ WRITE_ONCE(xdna->dev_handle->last_signal_ts, jiffies);
}
static bool aie2_tdr_detect(struct amdxdna_dev *xdna)
{
struct amdxdna_dev_hdl *ndev = xdna->dev_handle;
+ unsigned long last = READ_ONCE(ndev->last_signal_ts);
- if (READ_ONCE(ndev->tdr_status) == AIE2_TDR_WAIT) {
- XDNA_ERR(xdna, "TDR timeout detected");
- return true;
- }
+ if (!tdr_timeout_ms)
+ return false;
+
+ if (!time_after(jiffies, last + msecs_to_jiffies(tdr_timeout_ms)))
+ return false;
- WRITE_ONCE(ndev->tdr_status, AIE2_TDR_WAIT);
- return false;
+ XDNA_ERR(xdna, "TDR timeout detected");
+ return true;
}
static void aie2_cmd_release(struct kref *ref)
mmput(job->mm);
fence = ERR_PTR(ret);
} else {
+ /*
+ * Command is successfully posted to hardware, update the
+ * tdr timestamp. The total pending commands are limited.
+ * So there will not be a case that driver keeps posting
+ * commands without getting any hardware respond.
+ */
aie2_tdr_signal(hwctx->client->xdna);
}
trace_xdna_job(sched_job, hwctx->name, "sent to device",
const struct drm_sched_init_args args = {
.ops = &sched_ops,
.credit_limit = HWCTX_MAX_CMDS,
- .timeout = msecs_to_jiffies(tdr_timeout_ms),
+ .timeout = tdr_timeout_ms ?
+ msecs_to_jiffies(tdr_timeout_ms) :
+ MAX_SCHEDULE_TIMEOUT,
.name = "amdxdna_js",
.dev = xdna->ddev.dev,
};
u32 (*get_chain_msg_op)(u32 cmd_op);
};
-enum aie2_tdr_status {
- AIE2_TDR_WAIT,
- AIE2_TDR_SIGNALED,
-};
-
struct amdxdna_dev_hdl {
struct aie_device aie;
const struct amdxdna_dev_priv *priv;
u32 hwctx_num;
struct amdxdna_async_error last_async_err;
- enum aie2_tdr_status tdr_status;
+ unsigned long last_signal_ts;
};
struct aie2_hw_ops {