target/119010 - fixup zn4zn5 reservation for move from const_vector

movv8si_internal uses sselog1 and V4SFmode for an instruction like

(insn 363 2437 371 97 (set (reg:V8SI 46 xmm10 [1125])
        (const_vector:V8SI [
                (const_int 0 [0]) repeated x8
            ])) "ComputeNonbondedUtil.C":185:21 2402 {movv8si_internal}

this wasn't catched by the existing znver4_sse_log1 reservation,
I think the znver automaton catches this with the generic

(define_insn_reservation "znver1_sse_log1" 1
             (and (eq_attr "cpu" "znver1,znver2,znver3")
                  (and (eq_attr "type" "sselog1")
                   (eq_attr "memory" "none")))
             "znver1-direct,znver1-fp1|znver1-fp2")

which does not look at the mode at all.  The zn4zn5 automaton lacks
this and instead has separated store and load-store reservations
in odd ways.  The following renames the store one and introduces
a none variant.

	PR target/119010
	* config/i386/zn4zn5.md (znver4_sse_log1): Rename to
	znver4_sse_log1_store.
	(znver5_sse_log1): Rename to znver5_sse_log1_store.
	(znver4_sse_log1): New memory-less variant.

diff --git a/gcc/config/i386/zn4zn5.md b/gcc/config/i386/zn4zn5.md
index 75e3102021502390bfb4bd7a66c1e445b244c978..fb856e9dc988ab66588aa2bd4b2f5e3a0618cbbe 100644 (file)
--- a/gcc/config/i386/zn4zn5.md
+++ b/gcc/config/i386/zn4zn5.md
@@ -893,13 +893,20 @@
                         "znver4-direct,znver5-load,znver4-fpu")
 
 (define_insn_reservation "znver4_sse_log1" 1
+                        (and (eq_attr "cpu" "znver4,znver5")
+                             (and (eq_attr "type" "sselog1")
+                                  (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")
+                                   (eq_attr "memory" "none"))))
+                        "znver4-direct,znver4-fpu1|znver4-fpu2")
+
+(define_insn_reservation "znver4_sse_log1_store" 1
                         (and (eq_attr "cpu" "znver4")
                              (and (eq_attr "type" "sselog1")
                                   (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")
                                    (eq_attr "memory" "store"))))
                         "znver4-direct,znver4-fpu1|znver4-fpu2,znver4-fp-store")
 
-(define_insn_reservation "znver5_sse_log1" 1
+(define_insn_reservation "znver5_sse_log1_store" 1
                         (and (eq_attr "cpu" "znver5")
                              (and (eq_attr "type" "sselog1")
                                   (and (eq_attr "mode" "V4SF,V8SF,V2DF,V4DF,QI,HI,SI,DI,TI,OI")