arm64: dts: qcom: sm6125: Add dispcc node

Enable and configure the dispcc node on SM6125 for consumption by MDSS
later on.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-15-a3f287dd6c07@somainline.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index beccabcc985c25f27f3df35a739a32044e889d29..91b1a30481881a4ae66634c616b18d0113faed94 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
  */
 
+#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
@@ -1207,6 +1208,34 @@
                        reg = <0x04690000 0x10000>;
                };
 
+               dispcc: clock-controller@5f00000 {
+                       compatible = "qcom,sm6125-dispcc";
+                       reg = <0x05f00000 0x20000>;
+
+                       clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <&gcc GCC_DISP_AHB_CLK>,
+                                <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+                       clock-names = "bi_tcxo",
+                                     "dsi0_phy_pll_out_byteclk",
+                                     "dsi0_phy_pll_out_dsiclk",
+                                     "dsi1_phy_pll_out_dsiclk",
+                                     "dp_phy_pll_link_clk",
+                                     "dp_phy_pll_vco_div_clk",
+                                     "cfg_ahb_clk",
+                                     "gcc_disp_gpll0_div_clk_src";
+
+                       required-opps = <&rpmpd_opp_ret>;
+                       power-domains = <&rpmpd SM6125_VDDCX>;
+
+                       #clock-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                apps_smmu: iommu@c600000 {
                        compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
                        reg = <0x0c600000 0x80000>;