Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
gcc/ChangeLog:
* config/riscv/sync.md: Change LR.aq/SC.rl pairs into
sequentially consistent LR.aqrl/SC.rl pairs.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
"TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
{
return "1:\;"
- "lr.w.aq\t%0, %1\;"
+ "lr.w.aqrl\t%0, %1\;"
"<insn>\t%5, %0, %2\;"
"and\t%5, %5, %3\;"
"and\t%6, %0, %4\;"
"TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
{
return "1:\;"
- "lr.w.aq\t%0, %1\;"
+ "lr.w.aqrl\t%0, %1\;"
"and\t%5, %0, %2\;"
"not\t%5, %5\;"
"and\t%5, %5, %3\;"
"TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
{
return "1:\;"
- "lr.w.aq\t%0, %1\;"
+ "lr.w.aqrl\t%0, %1\;"
"and\t%4, %0, %3\;"
"or\t%4, %4, %2\;"
"sc.w.rl\t%4, %4, %1\;"
"TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
{
return "1:\;"
- "lr.w.aq\t%0, %1\;"
+ "lr.w.aqrl\t%0, %1\;"
"and\t%6, %0, %4\;"
"bne\t%6, %z2, 1f\;"
"and\t%6, %0, %5\;"