pinctrl: renesas: rzt2h: Allow .get_direction() for IRQ function GPIOs

Setting up an IRQ would normally be done in the .activate() and
.deactivate() ops of the IRQ domain, but for hierarchical IRQ domains
the .activate() and .deactivate() ops are overridden in the
gpiochip_hierarchy_setup_domain_ops() function.

As such, activating and deactivating need to be done in the .translate()
and .free() ops of the IRQ domain.

For RZ/T2H and RZ/N2H, interrupts go through the pin controller, into
the ICU, which level-translates them and forwards them to the GIC.

To use a GPIO as an interrupt it needs to be put into peripheral
function mode 0, which will connect it to the IRQ lines of the ICU.

The IRQ chip .child_to_parent_hwirq() callback is called as part of the
IRQ fwspec parsing logic (as part of irq_create_of_mapping()) which
happens before the IRQ is requested (as part of gpiochip_lock_as_irq()).

gpiochip_lock_as_irq() calls gpiod_get_direction() if the
.get_direction() callback is provided to ensure that the GPIO line is
set up as input.

In our case, IRQ function is separate from GPIO, and both cannot be true
at the same time.

Return GPIO_LINE_DIRECTION_IN even if pin is in IRQ function to allow
this setup to work.

Hold the spinlock to ensure atomicity between reading the PMC register
(which determines whether the pin is in GPIO mode or not) and reading
the function of the pin when it is not in GPIO mode.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251205150234.2958140-3-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
index c8ca5e13bba7cb5f027be545c973139782f63b1b..722551723e06a2b6626e6947af31febeba1315df 100644 (file)
--- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
@@ -51,6 +51,7 @@
 
 #define PFC_MASK               GENMASK_ULL(5, 0)
 #define PFC_PIN_MASK(pin)      (PFC_MASK << ((pin) * 8))
+#define PFC_FUNC_INTERRUPT     0
 
 /*
  * Use 16 lower bits [15:0] for pin identifier
@@ -494,6 +495,7 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
        struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
        u8 port = RZT2H_PIN_ID_TO_PORT(offset);
        u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
+       u64 reg64;
        u16 reg;
        int ret;
 
@@ -501,8 +503,25 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
        if (ret)
                return ret;
 
-       if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit))
+       guard(spinlock_irqsave)(&pctrl->lock);
+
+       if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) {
+               /*
+                * When a GPIO is being requested as an IRQ, the pinctrl
+                * framework expects to be able to read the GPIO's direction.
+                * IRQ function is separate from GPIO, and enabling it takes the
+                * pin out of GPIO mode.
+                * At this point, .child_to_parent_hwirq() has already been
+                * called to enable the IRQ function.
+                * Default to input direction for IRQ function.
+                */
+               reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
+               reg64 = (reg64 >> (bit * 8)) & PFC_MASK;
+               if (reg64 == PFC_FUNC_INTERRUPT)
+                       return GPIO_LINE_DIRECTION_IN;
+
                return -EINVAL;
+       }
 
        reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
        reg = (reg >> (bit * 2)) & PM_MASK;