Add extended pcie 64-bit access method to register access block.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
struct amdgpu_reg_access reg;
/* protects concurrent PCIE register access */
spinlock_t pcie_idx_lock;
- amdgpu_rreg64_ext_t pcie_rreg64_ext;
- amdgpu_wreg64_ext_t pcie_wreg64_ext;
struct amdgpu_doorbell doorbell;
/* clock/pll info */
#define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v))
#define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg))
#define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v))
-#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
-#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
+#define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg))
+#define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v))
#define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg))
#define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v))
#define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg))
return adev->nbio.funcs->get_rev_id(adev);
}
-static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
-{
- dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg);
- BUG();
- return 0;
-}
-
-static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
-{
- dev_err(adev->dev,
- "Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",
- reg, v);
- BUG();
-}
-
static uint32_t amdgpu_device_get_vbios_flags(struct amdgpu_device *adev)
{
if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
amdgpu_reg_access_init(adev);
- adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext;
- adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext;
-
dev_info(
adev->dev,
"initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
adev->reg.pcie.wreg_ext = NULL;
adev->reg.pcie.rreg64 = NULL;
adev->reg.pcie.wreg64 = NULL;
+ adev->reg.pcie.rreg64_ext = NULL;
+ adev->reg.pcie.wreg64_ext = NULL;
adev->reg.pcie.port_rreg = NULL;
adev->reg.pcie.port_wreg = NULL;
}
adev->reg.pcie.wreg64(adev, reg, v);
}
+uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg)
+{
+ if (!adev->reg.pcie.rreg64_ext) {
+ dev_err_once(adev->dev, "PCIE EXT 64-bit register read not supported\n");
+ return 0;
+ }
+ return adev->reg.pcie.rreg64_ext(adev, reg);
+}
+
+void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg,
+ uint64_t v)
+{
+ if (!adev->reg.pcie.wreg64_ext) {
+ dev_err_once(adev->dev, "PCIE EXT 64-bit register write not supported\n");
+ return;
+ }
+ adev->reg.pcie.wreg64_ext(adev, reg, v);
+}
+
uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg)
{
if (!adev->reg.pcie.port_rreg) {
typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t);
typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t);
typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t);
+typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t);
+typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t);
typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t,
uint32_t);
amdgpu_wreg_ext_t wreg_ext;
amdgpu_rreg64_t rreg64;
amdgpu_wreg64_t wreg64;
+ amdgpu_rreg64_ext_t rreg64_ext;
+ amdgpu_wreg64_ext_t wreg64_ext;
amdgpu_rreg_t port_rreg;
amdgpu_wreg_t port_wreg;
};
uint32_t v);
uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v);
+uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg);
+void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg,
+ uint64_t v);
uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg,
uint32_t v);
-typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t);
-typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t);
-
uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
uint32_t acc_flags);
uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg,
adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext;
adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64;
adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64;
- adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext;
- adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext;
+ adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext;
+ adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext;
adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg;
adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg;
adev->reg.didt.rreg = &soc15_didt_rreg;
adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64;
adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg;
adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg;
- adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext;
- adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext;
+ adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext;
+ adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext;
adev->asic_funcs = &soc_v1_0_asic_funcs;