]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
serial: qcom-geni: move resource initialization to separate function
authorPraveen Talari <quic_ptalari@quicinc.com>
Mon, 21 Jul 2025 17:45:28 +0000 (23:15 +0530)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 22 Jul 2025 16:52:50 +0000 (18:52 +0200)
Enhances code readability and future modifications within the new API.

Move the code that handles the actual initialization of resources
like clock and ICC paths to a separate function, making the
probe function cleaner.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Praveen Talari <quic_ptalari@quicinc.com>
Link: https://lore.kernel.org/r/20250721174532.14022-5-quic_ptalari@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/tty/serial/qcom_geni_serial.c

index 004f9a0d80f734dd00b077d753388e026b86f15a..1e1c60d7aceda8c5b8c04ca9dfc93fd11e594ba3 100644 (file)
@@ -1619,6 +1619,43 @@ static struct uart_driver qcom_geni_uart_driver = {
        .nr =  GENI_UART_PORTS,
 };
 
+static int geni_serial_resource_init(struct qcom_geni_serial_port *port)
+{
+       int ret;
+
+       port->se.clk = devm_clk_get(port->se.dev, "se");
+       if (IS_ERR(port->se.clk)) {
+               ret = PTR_ERR(port->se.clk);
+               dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret);
+               return ret;
+       }
+
+       ret = geni_icc_get(&port->se, NULL);
+       if (ret)
+               return ret;
+
+       port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
+       port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
+
+       /* Set BW for register access */
+       ret = geni_icc_set_bw(&port->se);
+       if (ret)
+               return ret;
+
+       ret = devm_pm_opp_set_clkname(port->se.dev, "se");
+       if (ret)
+               return ret;
+
+       /* OPP table is optional */
+       ret = devm_pm_opp_of_add_table(port->se.dev);
+       if (ret && ret != -ENODEV) {
+               dev_err(port->se.dev, "invalid OPP table in device tree\n");
+               return ret;
+       }
+
+       return 0;
+}
+
 static void qcom_geni_serial_pm(struct uart_port *uport,
                unsigned int new_state, unsigned int old_state)
 {
@@ -1739,12 +1776,10 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
        port->dev_data = data;
        port->se.dev = &pdev->dev;
        port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
-       port->se.clk = devm_clk_get(&pdev->dev, "se");
-       if (IS_ERR(port->se.clk)) {
-               ret = PTR_ERR(port->se.clk);
-               dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
+
+       ret = geni_serial_resource_init(port);
+       if (ret)
                return ret;
-       }
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!res)
@@ -1764,17 +1799,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
                        return -ENOMEM;
        }
 
-       ret = geni_icc_get(&port->se, NULL);
-       if (ret)
-               return ret;
-       port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
-       port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
-
-       /* Set BW for register access */
-       ret = geni_icc_set_bw(&port->se);
-       if (ret)
-               return ret;
-
        port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
                        "qcom_geni_serial_%s%d",
                        uart_console(uport) ? "console" : "uart", uport->line);
@@ -1796,16 +1820,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
        if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
                port->cts_rts_swap = true;
 
-       ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
-       if (ret)
-               return ret;
-       /* OPP table is optional */
-       ret = devm_pm_opp_of_add_table(&pdev->dev);
-       if (ret && ret != -ENODEV) {
-               dev_err(&pdev->dev, "invalid OPP table in device tree\n");
-               return ret;
-       }
-
        port->private_data.drv = drv;
        uport->private_data = &port->private_data;
        platform_set_drvdata(pdev, port);