ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC

Add RTT support for SAMA7D65 SoC. The GPBR is added so the SoC is able
to store the RTT time data.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Link: https://lore.kernel.org/r/e8868ef06102241b47883ba10edaed751831be6d.1744666011.git.Ryan.Wanner@microchip.com
[claudiu.beznea: keep nodes sorted by their address]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index f93978e98ac22fcf9101f204d39ad5cfb75f9d23..d08d773b1cc578fc6a713922497facac429c2c01 100644 (file)
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -132,6 +132,13 @@
                        status = "disabled";
                };
 
+               rtt: rtc@e001d300 {
+                       compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
+                       reg = <0xe001d300 0x30>;
+                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk32k 0>;
+               };
+
                clk32k: clock-controller@e001d500 {
                        compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
                        reg = <0xe001d500 0x4>;
@@ -139,6 +146,11 @@
                        #clock-cells = <1>;
                };
 
+               gpbr: syscon@e001d700 {
+                       compatible = "microchip,sama7d65-gpbr", "syscon";
+                       reg = <0xe001d700 0x48>;
+               };
+
                rtc: rtc@e001d800 {
                        compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc";
                        reg = <0xe001d800 0x30>;