testsuite: arm: Disable sched2 and sched3 in unsigned-extend-2.c

Disable sched2 and sched3 to only have one order of instructions to
consider.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/unsigned-extend-2.c: Disable sched2 and sched3
	and update function body to match.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
index d9f95a14277b261907322e7ad2449a3abcdd38a6..8a1a293bc95a7705b885f74b9c3162fa4531b16b 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
+++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
@@ -1,26 +1,21 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_thumb2_ok } */
-/* { dg-options "-O2 -mthumb" } */
+/* { dg-options "-O2 -mthumb  -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*
 ** foo:
-**     movs    (r[0-9]+), #8
 ** (
-**     subs    \1, \1, #1
-**     ands    \1, \1, #255
+**     movs    (r[0-9]+), #8
 **     and     r0, r1, r0, lsr #1
-**     bne     .L[0-9]+
-**     bx      lr
-** |
 **     subs    \1, \1, #1
-**     and     r0, r1, r0, lsr #1
 **     ands    \1, \1, #255
 **     bne     .L[0-9]+
 **     bx      lr
 ** |
 **     push    {lr}
-**     dls     lr, \1
+**     movs    (r[0-9]+), #8
+**     dls     lr, \2
 **     and     r0, r1, r0, lsr #1
 **     le      lr, .L[0-9]+
 **     pop     {pc}