RISC-V: Add Types to Un-Typed Vector Instructions

Updates vector instructions to ensure that no instruction is left
without a type attribute. Create a placeholder type "vector" for
instructions where a type isn't clear

Tested for regressions using rv32/rv64 gc/gcv multilib with newlib/linux.

gcc/Changelog:

	* config/riscv/autovec-vls.md: Update types
	* config/riscv/riscv.md: Add vector placeholder type
	* config/riscv/vector.md: Update types

Reviewed-by: Jeff Law <jlaw@ventanamicro.com>
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>

diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 1b1d940d779b122ad5507dcb8fc11cfdc8a515bc..35b86de25c7173fe9d8281f1be84e363f83bde53 100644 (file)
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -68,6 +68,7 @@
       }
     DONE;
   }
+  [(set_attr "type" "vmov")]
 )
 
 (define_insn_and_split "*mov<mode>"
@@ -89,6 +90,7 @@
     gcc_assert (ok_p);
     DONE;
   }
+  [(set_attr "type" "vmov")]
 )
 
 (define_expand "mov<mode>"
@@ -130,7 +132,9 @@
                                        riscv_vector::RVV_UNOP, operands, operands[2]);
     }
   DONE;
-})
+}
+  [(set_attr "type" "vmov")]
+)
 
 (define_insn "*mov<mode>_vls"
   [(set (match_operand:VLS 0 "register_operand" "=vr")
@@ -157,6 +161,7 @@
                                    riscv_vector::RVV_UNOP, operands);
     DONE;
   }
+  [(set_attr "type" "vector")]
 )
 
 ;; -------------------------------------------------------------------------
@@ -180,7 +185,9 @@
   riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
                                 riscv_vector::RVV_BINOP, operands);
   DONE;
-})
+}
+[(set_attr "type" "vector")]
+)
 
 ;; -------------------------------------------------------------------------------
 ;; ---- [INT] Unary operations
@@ -201,4 +208,6 @@
   insn_code icode = code_for_pred (<CODE>, <MODE>mode);
   riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
   DONE;
-})
+}
+[(set_attr "type" "vector")]
+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 87f4a4a33f98ce04df970f2b1c2257a8e2a4e13d..0127b9e5abbdda414dc3691ae4d1e9e13431c74f 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -410,6 +410,7 @@
 ;; vgather      vector register gather instructions
 ;; vcompress    vector compress instruction
 ;; vmov         whole vector register move
+;; vector       unknown vector instruction
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
@@ -429,7 +430,7 @@
    vired,viwred,vfredu,vfredo,vfwredu,vfwredo,
    vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,
    vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,
-   vgather,vcompress,vmov"
+   vgather,vcompress,vmov,vector"
   (cond [(eq_attr "got" "load") (const_string "load")
 
         ;; If a doubleword move uses these expensive instructions,

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index d6bfbe81fccced25e92377865bf00e2f385cf202..27901c4692cc23e8ef3bf95d4aef40dcf56c1c9d 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -878,13 +878,15 @@
   [(set (match_operand:V 0 "register_operand" "=vr")
        (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
   "TARGET_VECTOR"
-  "")
+  ""
+  [(set_attr "type" "vector")])
 
 (define_insn "@vundefined<mode>"
   [(set (match_operand:VB 0 "register_operand" "=vr")
        (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
   "TARGET_VECTOR"
-  "")
+  ""
+  [(set_attr "type" "vector")])
 
 (define_expand "@vreinterpret<mode>"
   [(set (match_operand:V 0 "register_operand")
@@ -935,7 +937,8 @@
   [(set (match_operand:P 0 "register_operand" "=r")
        (unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))]
   "TARGET_VECTOR"
-  "")
+  ""
+  [(set_attr "type" "vector")])
 
 ;; Set VXRM
 (define_insn "vxrmsi"
@@ -1135,7 +1138,9 @@
                                     riscv_vector::RVV_UNOP, operands, operands[2]);
     }
   DONE;
-})
+}
+[(set_attr "type" "vector")]
+)
 
 (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
   [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
@@ -1155,7 +1160,9 @@
                                     riscv_vector::RVV_UNOP, operands, operands[2]);
     }
   DONE;
-})
+}
+[(set_attr "type" "vector")]
+)
 
 ;; Define tuple modes data movement.
 ;; operands[2] is used to save the offset of each subpart.