PCI: rzg3s-host: Use pci_generic_config_write() for the root bus

The Renesas RZ/G3S host controller allows writing to read-only PCIe
configuration registers when the RZG3S_PCI_PERM_CFG_HWINIT_EN bit is set in
the RZG3S_PCI_PERM register. However, callers of struct pci_ops::write
expect the semantics defined by the PCIe specification, meaning that writes
to read-only registers must not be allowed.

The previous custom struct pci_ops::write implementation for the root bus
temporarily enabled write access before calling pci_generic_config_write().
This breaks the expected semantics.

Remove the custom implementation and simply use pci_generic_config_write().

Along with this change, the updates of the PCI_PRIMARY_BUS,
PCI_SECONDARY_BUS, and PCI_SUBORDINATE_BUS registers were moved so that
they no longer depends on the RZG3S_PCI_PERM_CFG_HWINIT_EN bit in the
RZG3S_PCI_PERM_CFG register, since these registers are R/W.

Fixes: 7ef502fb35b2 ("PCI: Add Renesas RZ/G3S host controller driver")
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://patch.msgid.link/20251217111510.138848-2-claudiu.beznea.uj@bp.renesas.com

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index 83ec66a7082361af8bbfd04ba49417a5877d53e2..ae6d9c7dc2c1224534b03fa3768cc874d1e368ac 100644 (file)
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -439,28 +439,9 @@ static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus,
        return host->pcie + where;
 }
 
-/* Serialized by 'pci_lock' */
-static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
-                                int where, int size, u32 val)
-{
-       struct rzg3s_pcie_host *host = bus->sysdata;
-       int ret;
-
-       /* Enable access control to the CFGU */
-       writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
-                      host->axi + RZG3S_PCI_PERM);
-
-       ret = pci_generic_config_write(bus, devfn, where, size, val);
-
-       /* Disable access control to the CFGU */
-       writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
-
-       return ret;
-}
-
 static struct pci_ops rzg3s_pcie_root_ops = {
        .read           = pci_generic_config_read,
-       .write          = rzg3s_pcie_root_write,
+       .write          = pci_generic_config_write,
        .map_bus        = rzg3s_pcie_root_map_bus,
 };
 
@@ -1065,14 +1046,14 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)
        writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);
        writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);
 
+       /* Disable access control to the CFGU */
+       writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
+
        /* Update bus info */
        writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS);
        writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS);
        writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS);
 
-       /* Disable access control to the CFGU */
-       writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
-
        return 0;
 }