arm64: dts: imx8mp: configure GPU and NPU clocks in nominal DTSI

Commit 255fbd9eabe7 ("arm64: dts: imx8mp: Add optional nominal drive
mode DTSI") added imx8mp-nominal.dtsi, which overrides all overdrive
clock rates in imx8mp.dtsi to the nominal rates.

At the same time, commit 9f7595b3e5ae ("arm64: dts: imx8mp: configure
GPU and NPU clocks to overdrive rate") went in, which changed some
clock rates away from the nominal values.

Resolve the discrepancy by effectively reverting the changes in the
latter commit inside imx8mp-nominal.dtsi. This is required for proper
operation of the imx8mp-skov boards, which are currently
imx8mp-nominal.dtsi's only users and lets all other boards that don't
include it benefit from the new higher frequencies.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi
index a1b75c9068b288a2fba73bbd96b1519a50df85a3..dc0ccd723c6d92e7946ebd52bac535e4175498d0 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-nominal.dtsi
@@ -24,6 +24,20 @@
        fsl,operating-mode = "nominal";
 };
 
+&gpu2d {
+       assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+       assigned-clock-rates = <800000000>;
+};
+
+&gpu3d {
+       assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
+                         <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+                                <&clk IMX8MP_SYS_PLL1_800M>;
+       assigned-clock-rates = <800000000>, <800000000>;
+};
+
 &pgc_hdmimix {
        assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
                          <&clk IMX8MP_CLK_HDMI_APB>;
@@ -46,6 +60,18 @@
        assigned-clock-rates = <600000000>, <300000000>;
 };
 
+&pgc_mlmix {
+       assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
+                         <&clk IMX8MP_CLK_ML_AXI>,
+                         <&clk IMX8MP_CLK_ML_AHB>;
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+                                <&clk IMX8MP_SYS_PLL1_800M>,
+                                <&clk IMX8MP_SYS_PLL1_800M>;
+       assigned-clock-rates = <800000000>,
+                              <800000000>,
+                              <300000000>;
+};
+
 &media_blk_ctrl {
        assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
                          <&clk IMX8MP_CLK_MEDIA_APB>,