wifi: rtw89: pci: warn if SPS OCP happens for RTL8922DE

SPS OCP (over current protection) is a mechanism to cut off power to
protect hardware. When this happens, raise an interrupt to signal driver,
which prints out a message to note hardware status.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260127085036.44060-7-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c
index fb4469a76bc03bf0950bc4939a9a8bbd08ac807a..43c61b3dc969f259100a96cbde16d50dd469c1b9 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.c
+++ b/drivers/net/wireless/realtek/rtw89/pci.c
@@ -970,6 +970,9 @@ static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev)
        if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_wdt_timeout))
                rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT);
 
+       if (unlikely(isrs.halt_c2h_isrs & isr_def->isr_sps_ocp))
+               rtw89_warn(rtwdev, "SPS OCP alarm 0x%x\n", isrs.halt_c2h_isrs);
+
        if (unlikely(rtwpci->under_recovery))
                goto enable_intr;
 
@@ -4005,7 +4008,8 @@ static void rtw89_pci_recovery_intr_mask_v3(struct rtw89_dev *rtwdev)
        struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
 
        rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0;
-       rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
+       rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN |
+                                B_BE_SPSANA_OCP_INT_EN | B_BE_SPS_OCP_INT_EN;
        rtwpci->intrs[0] = 0;
        rtwpci->intrs[1] = 0;
 }
@@ -4015,7 +4019,8 @@ static void rtw89_pci_default_intr_mask_v3(struct rtw89_dev *rtwdev)
        struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
 
        rtwpci->ind_intrs = B_BE_HS0_IND_INT_EN0;
-       rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN;
+       rtwpci->halt_c2h_intrs = B_BE_HALT_C2H_INT_EN | B_BE_WDT_TIMEOUT_INT_EN |
+                                B_BE_SPSANA_OCP_INT_EN | B_BE_SPS_OCP_INT_EN;
        rtwpci->intrs[0] = 0;
        rtwpci->intrs[1] = B_BE_PCIE_RDU_CH1_IMR |
                           B_BE_PCIE_RDU_CH0_IMR |
@@ -4657,6 +4662,7 @@ const struct rtw89_pci_isr_def rtw89_pci_isr_ax = {
        .isr_rdu = B_AX_RDU_INT,
        .isr_halt_c2h = B_AX_HALT_C2H_INT_EN,
        .isr_wdt_timeout = B_AX_WDT_TIMEOUT_INT_EN,
+       .isr_sps_ocp = 0,
        .isr_clear_rpq = {R_AX_PCIE_HISR00, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT},
        .isr_clear_rxq = {R_AX_PCIE_HISR00, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT |
                                            B_AX_RDU_INT},

diff --git a/drivers/net/wireless/realtek/rtw89/pci.h b/drivers/net/wireless/realtek/rtw89/pci.h
index b0081b6940468500bc3fa11940b490539ea6e089..ccfa6d33623aa3c9b3a1cb0716c6cfafbcc860f8 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci.h
+++ b/drivers/net/wireless/realtek/rtw89/pci.h
@@ -1331,6 +1331,7 @@ struct rtw89_pci_isr_def {
        u32 isr_rdu;
        u32 isr_halt_c2h;
        u32 isr_wdt_timeout;
+       u32 isr_sps_ocp;
        struct rtw89_reg2_def isr_clear_rpq;
        struct rtw89_reg2_def isr_clear_rxq;
 };

diff --git a/drivers/net/wireless/realtek/rtw89/pci_be.c b/drivers/net/wireless/realtek/rtw89/pci_be.c
index 33bdd3e66bf6e3aac6b5e48fb45d1ad53f371ddd..114f40c6c31bc03d1440a2571e6aed4d84096082 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/pci_be.c
+++ b/drivers/net/wireless/realtek/rtw89/pci_be.c
@@ -763,6 +763,7 @@ const struct rtw89_pci_isr_def rtw89_pci_isr_be = {
        .isr_rdu = B_BE_RDU_CH1_INT_V1 | B_BE_RDU_CH0_INT_V1,
        .isr_halt_c2h = B_BE_HALT_C2H_INT,
        .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT,
+       .isr_sps_ocp = 0,
        .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1},
        .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1},
 };
@@ -772,6 +773,7 @@ const struct rtw89_pci_isr_def rtw89_pci_isr_be_v1 = {
        .isr_rdu = B_BE_PCIE_RDU_CH1_INT | B_BE_PCIE_RDU_CH0_INT,
        .isr_halt_c2h = B_BE_HALT_C2H_INT,
        .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT,
+       .isr_sps_ocp = B_BE_SPS_OCP_INT | B_BE_SPSANA_OCP_INT,
        .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1},
        .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1},
 };