arm64: dts: freescale: imx8mm-var-som: Add MCP251xFD CAN controller

Add support for the Microchip MCP251xFD CAN-FD controller connected
to the SPI bus on the i.MX8MM VAR-SOM.

The controller uses a 40 MHz external oscillator and requires an
interrupt line and a dedicated RX interrupt GPIO.

Add the fixed clock, the MCP251xFD device node with the required
properties, and the corresponding pinctrl configuration.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
index 7cedef8add32f98834166324a66fb8966cdf98ad..749342b9a0a77ea0b3229cc531fa0aeb729e1a78 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi
@@ -14,6 +14,13 @@
                reg = <0x0 0x40000000 0 0x80000000>;
        };
 
+       clk40m: oscillator {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <40000000>;
+               clock-output-names = "can_osc";
+       };
+
        reg_audio_supply: regulator-3p3v {
                compatible = "regulator-fixed";
                regulator-name = "wm8904-supply";
@@ -139,6 +146,19 @@
                ti,keep-vref-on;
                wakeup-source;
        };
+
+       /* CAN controller */
+       can0: can@1 {
+               compatible = "microchip,mcp251xfd";
+               reg = <1>;
+               clocks = <&clk40m>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_can>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+               spi-max-frequency = <20000000>;
+               microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+       };
 };
 
 &fec1 {
@@ -424,6 +444,13 @@
 };
 
 &iomuxc {
+       pinctrl_can: cangrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5               0x16
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x16
+               >;
+       };
+
        pinctrl_ecspi1: ecspi1grp {
                fsl,pins = <
                        MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x13