int i;
/* Only supported on platforms that use atomic watermark design */
- if (!display->funcs.wm->optimize_watermarks)
+ if (!display->wm.funcs->optimize_watermarks)
return;
if (drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 9))
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(display)) {
ilk_setup_wm_latency(display);
- display->funcs.wm = &ilk_wm_funcs;
+ display->wm.funcs = &ilk_wm_funcs;
} else if (display->platform.valleyview || display->platform.cherryview) {
vlv_setup_wm_latency(display);
- display->funcs.wm = &vlv_wm_funcs;
+ display->wm.funcs = &vlv_wm_funcs;
} else if (display->platform.g4x) {
g4x_setup_wm_latency(display);
- display->funcs.wm = &g4x_wm_funcs;
+ display->wm.funcs = &g4x_wm_funcs;
} else if (display->platform.pineview) {
if (!pnv_get_cxsr_latency(display)) {
drm_info(display->drm, "Unknown FSB/MEM, disabling CxSR\n");
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(display, false);
- display->funcs.wm = &nop_funcs;
+ display->wm.funcs = &nop_funcs;
} else {
- display->funcs.wm = &pnv_wm_funcs;
+ display->wm.funcs = &pnv_wm_funcs;
}
} else if (DISPLAY_VER(display) == 4) {
- display->funcs.wm = &i965_wm_funcs;
+ display->wm.funcs = &i965_wm_funcs;
} else if (DISPLAY_VER(display) == 3) {
- display->funcs.wm = &i9xx_wm_funcs;
+ display->wm.funcs = &i9xx_wm_funcs;
} else if (DISPLAY_VER(display) == 2) {
if (INTEL_NUM_PIPES(display) == 1)
- display->funcs.wm = &i845_wm_funcs;
+ display->wm.funcs = &i845_wm_funcs;
else
- display->funcs.wm = &i9xx_wm_funcs;
+ display->wm.funcs = &i9xx_wm_funcs;
} else {
drm_err(display->drm,
"unexpected fall-through in %s\n", __func__);
- display->funcs.wm = &nop_funcs;
+ display->wm.funcs = &nop_funcs;
}
}
if (DISPLAY_VER(display) != 2)
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
- if (!display->funcs.wm->initial_watermarks)
+ if (!display->wm.funcs->initial_watermarks)
intel_update_watermarks(display);
/* clock the pipe down to 640x480@60 to potentially save power */
};
struct intel_wm {
+ /* internal watermark functions */
+ const struct intel_wm_funcs *funcs;
+
/*
* Raw watermark latency values:
* in 0.1us units for WM0,
/* irq display functions */
const struct intel_hotplug_funcs *hotplug;
-
- /* pm display functions */
- const struct intel_wm_funcs *wm;
} funcs;
struct {
*/
void intel_update_watermarks(struct intel_display *display)
{
- if (display->funcs.wm->update_wm)
- display->funcs.wm->update_wm(display);
+ if (display->wm.funcs->update_wm)
+ display->wm.funcs->update_wm(display);
}
int intel_wm_compute(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(state);
- if (!display->funcs.wm->compute_watermarks)
+ if (!display->wm.funcs->compute_watermarks)
return 0;
- return display->funcs.wm->compute_watermarks(state, crtc);
+ return display->wm.funcs->compute_watermarks(state, crtc);
}
bool intel_initial_watermarks(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(state);
- if (display->funcs.wm->initial_watermarks) {
- display->funcs.wm->initial_watermarks(state, crtc);
+ if (display->wm.funcs->initial_watermarks) {
+ display->wm.funcs->initial_watermarks(state, crtc);
return true;
}
{
struct intel_display *display = to_intel_display(state);
- if (display->funcs.wm->atomic_update_watermarks)
- display->funcs.wm->atomic_update_watermarks(state, crtc);
+ if (display->wm.funcs->atomic_update_watermarks)
+ display->wm.funcs->atomic_update_watermarks(state, crtc);
}
void intel_optimize_watermarks(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(state);
- if (display->funcs.wm->optimize_watermarks)
- display->funcs.wm->optimize_watermarks(state, crtc);
+ if (display->wm.funcs->optimize_watermarks)
+ display->wm.funcs->optimize_watermarks(state, crtc);
}
int intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
- if (display->funcs.wm->compute_global_watermarks)
- return display->funcs.wm->compute_global_watermarks(state);
+ if (display->wm.funcs->compute_global_watermarks)
+ return display->wm.funcs->compute_global_watermarks(state);
return 0;
}
void intel_wm_get_hw_state(struct intel_display *display)
{
- if (display->funcs.wm->get_hw_state)
- return display->funcs.wm->get_hw_state(display);
+ if (display->wm.funcs->get_hw_state)
+ return display->wm.funcs->get_hw_state(display);
}
void intel_wm_sanitize(struct intel_display *display)
{
- if (display->funcs.wm->sanitize)
- return display->funcs.wm->sanitize(display);
+ if (display->wm.funcs->sanitize)
+ return display->wm.funcs->sanitize(display);
}
bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
skl_setup_wm_latency(display);
- display->funcs.wm = &skl_wm_funcs;
+ display->wm.funcs = &skl_wm_funcs;
}
static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)