RISC-V: Use builtin for ffs and ffsll while supported extension available

Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb extension. With special `-march` flags defined, we can generate more simplified code compared to the generic implementation of `ffs`/`ffsll`.

Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>
Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>

diff --git a/sysdeps/riscv/math-use-builtins-ffs.h b/sysdeps/riscv/math-use-builtins-ffs.h
new file mode 100644 (file)
index 0000000..97d13e9
--- /dev/null
+++ b/sysdeps/riscv/math-use-builtins-ffs.h
@@ -0,0 +1,10 @@
+#if __GNUC_PREREQ (12, 0) && defined __riscv_zbb
+#  define USE_FFS_BUILTIN 1
+#  define USE_FFSLL_BUILTIN 1
+#elif __GNUC_PREREQ (13, 0) && defined __riscv_xtheadbb
+#  define USE_FFS_BUILTIN 0
+#  define USE_FFSLL_BUILTIN 1
+#else
+#  define USE_FFS_BUILTIN 0
+#  define USE_FFSLL_BUILTIN 0
+#endif