drm/amd/pm: Fix si_dpm mmCG_THERMAL_INT setting

Use WREG32 to write mmCG_THERMAL_INT.
This is a direct access register.

Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 2555f4e4a741d31e0496572a8ab4f55941b4e30e)

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 1f539cc65f41ffd65d9713c38d1670da79f80f23..9a6f4f584c1baa831f8006d9b2117bfb0b9869cb 100644 (file)
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -7600,12 +7600,12 @@ static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
                case AMDGPU_IRQ_STATE_DISABLE:
                        cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
                        cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
-                       WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+                       WREG32(mmCG_THERMAL_INT, cg_thermal_int);
                        break;
                case AMDGPU_IRQ_STATE_ENABLE:
                        cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
                        cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK;
-                       WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+                       WREG32(mmCG_THERMAL_INT, cg_thermal_int);
                        break;
                default:
                        break;
@@ -7617,12 +7617,12 @@ static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
                case AMDGPU_IRQ_STATE_DISABLE:
                        cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
                        cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
-                       WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+                       WREG32(mmCG_THERMAL_INT, cg_thermal_int);
                        break;
                case AMDGPU_IRQ_STATE_ENABLE:
                        cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);
                        cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK;
-                       WREG32_SMC(mmCG_THERMAL_INT, cg_thermal_int);
+                       WREG32(mmCG_THERMAL_INT, cg_thermal_int);
                        break;
                default:
                        break;