The RZ/G3E RSCI IP has 32-stage FIFO compared to 16-stage FIFO on RZ/T2H.
Add RSCI_PORT_SCIF32 port ID to differentiate it from RZ/T2H RSCI and
update sci_is_rsci_type() and sci_is_fifo_type()
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20251129164325.209213-13-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
/* Private port IDs */
enum SCI_PORT_TYPE {
RSCI_PORT_SCIF16 = BIT(7) | 0,
+ RSCI_PORT_SCIF32 = BIT(7) | 1,
};
enum SCI_CLKS {
static bool sci_is_rsci_type(u8 type)
{
- return (type == RSCI_PORT_SCIF16);
+ return (type == RSCI_PORT_SCIF16 || type == RSCI_PORT_SCIF32);
}
static int sci_handle_fifo_overrun(struct uart_port *port)