Update bug status.

diff --git a/NEWS b/NEWS
index 69318782cf55f02941461e6f7103db994739b52f..42c29cbd10efaa405f579d9c884078689a7426be 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -87,8 +87,9 @@ where XXXXXX is the bug number as listed below.
 384230  vex x86->IR: unhandled instruction bytes: 0x67 0xE8 0xAB 0x68
         == 384156  vex x86->IR: unhandled instruction bytes: 0x67 0xE8 0x6B 0x6A
 
-384526  reduce number of spill instructions generated by VEX register allocator v3
-384584  Callee saved registers listed first for AMD64, X86, and PPC architectures
+384526  reduce number of spill insns generated by VEX register allocator v3
+384584  Callee saved regs listed first for AMD64, X86, and PPC architectures
+384631  Sanitise client args as printed with -v
 384633  Add a simple progress-reporting facility
 384987  VEX register allocator: allocate caller-save registers for short lived vregs
 385182  PPC64 is missing support for the DSCR
@@ -120,6 +121,7 @@ where XXXXXX is the bug number as listed below.
 393099  posix_memalign() invalid write if alignment == 0
 395709  PPC64 is missing support for the xvnegsp instruction
 395682  Accept read-only PT_LOAD segments and .rodata by ld -z separate-code
+        == 384727
 
 n-i-bz  Fix missing workq_ops operations (macOS)
 n-i-bz  fix bug in strspn replacement

diff --git a/docs/internals/3_13_BUGSTATUS.txt b/docs/internals/3_13_BUGSTATUS.txt
index 48c4b980adfc629acace44677a4256c03b0c84ed..d7338148d3a7a92864f17962ce19f909afeec9ab 100644 (file)
--- a/docs/internals/3_13_BUGSTATUS.txt
+++ b/docs/internals/3_13_BUGSTATUS.txt
@@ -126,6 +126,9 @@ Possibly easy fix; queried.  NB: pertains to V syscalls, not the client.
 383901  PTP_ENABLE_PPS ioctl
 Has patch, but looks rather big for what seems like a small problem
 
+384732  posix_spawn with glibc 2.25 causes an assertion
+Looks possibly serious, but also a bit old.  Is this still relevant?
+
 === KernelInterface/OS X ===============================================
 
 (carried over)
@@ -331,6 +334,9 @@ Wishlist, low prio
         to implement masking and shifting (x86_64)
 Doesn't seem like a widespread problem
 
+384661  after make install 476 errors from five contexts on OS 10.12.5
+General OS X badness, probably not actionable
+
 === Tools/SGCheck ======================================================
 
 === Uncategorised ======================================================
@@ -364,6 +370,9 @@ Doesn't seem like a widespread problem
 383811  Failure to build on macOS 10.13 High Sierra (OS X)
         == 385910  clang level not detected on OS X Sierra for Xcode 9
 
+384729  __libc_freeres inhibits cross-platform valgrind
+Wishlist
+
 === Uncategorised/run ==================================================
 
 (carried over)
@@ -393,6 +402,9 @@ Doesn't seem like a widespread problem
 (carried over)
 379273  Phone restarts when run with valgrind
 
+384630  The 'impossible' happened (__ubsan_handle_shift_out_of_bounds) as soon
+        as starting anything under valgrind
+
 === VEX ================================================================
 === VEX/amd64 ==========================================================
 
@@ -467,6 +479,10 @@ n-i-bz  Remove limit on strd's negative immediates
 384442  ARM: bad pc in complaint if instruction changes pc
 Earlywriteback problems; low prio
 
+384808  disInstr(arm): unhandled instruction: 0xEF9F0002
+        (svc #0x9f0002,sys_cacheflush for ARM Linux)
+Reported in 3.12, may be fixed now?
+
 === VEX/arm64 ==========================================================
 
 (carried over)
@@ -483,6 +499,12 @@ Legit, but low prio
 
 === VEX/other ==========================================================
 
+384681  PUT(pc, <variable>) should specialize to help debugging
+Wishlist
+
+384842  Reporting for VEX IR semantic bugs
+This does actually show 3 problems which look ungood!
+
 === VEX/ppc ============================================================
 
 (carried over)
@@ -650,23 +672,8 @@ Wed 10 May 10:24:16 CEST 2017
 384337  performance improvements to VEX register allocator v2 and v3
 ** I think this can be closed.  Queried Ivo.
 
-384526  reduce number of spill instructions in VEX register allocator v3
-384584  list first callee saved registers for AMD64, X86, and PPC architectures
-384630  The 'impossible' happened (__ubsan_handle_shift_out_of_bounds) as soon
-        as starting anything under valgrind
-384631  Sanitise client args as printed with -v
-384633  Add a simple progress-reporting facility
-384661  after make install 476 errors from five contexts on OS 10.12.5
-384676  VEX AMD64 backend should list more real registers as available for
-        the register allocator
-384681  PUT(pc, <variable>) should specialize to help debugging
-384727  valgrind does not support debug info for read only segments
-        (generated by LLD)
-384729  __libc_freeres inhibits cross-platform valgrind
-384732  posix_spawn with glibc 2.25 causes an assertion
-384808  disInstr(arm): unhandled instruction: 0xEF9F0002
-        (svc #0x9f0002,sys_cacheflush for ARM Linux)
-384842  Reporting for VEX IR semantic bugs
+Fri 27 Jul 17:22:10 CEST 2018
+
 384877  (ARM64) Added translation for instruction LDRSW (literal)
 384930  Valgrind fails to compute correctly some code using the GMP library
 384959  Incorrect jumpkind for arm instruction - LDR PC, [SP],#4
@@ -843,4 +850,4 @@ Tue 24 Jul 11:50:41 CEST 2018
 
 Also: make arm32 resume with sigcontext regs after signal return (395991)
 
-396839] New: s390x: Trap instructions not implemented
+396839  s390x: Trap instructions not implemented