net: dsa: mv88e6xxx: add field to specify internal phys layout

[ Upstream commit 3ba89b28adb21a5d5d78e905e2c3972816606bb4 ]

mv88e6xxx currently assumes that switch equipped with internal phys have
those phys mapped contiguously starting from port 0 (see
mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
integrated PHYs available on ports 1 to 8
To properly support this offset, add a new field to allow specifying an
internal PHYs layout. If field is not set, default layout is assumed (start
at port 0)

Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Stable-dep-of: 52fdc41c3278 ("net: dsa: mv88e6xxx: fix internal PHYs for 6320 family")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index cabf97a902b52f46af46e5c271a7eaa91ea2ce1f..c1a322d6432c01c3b7a15b65ece1b31fa9eefe2e 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -472,7 +472,9 @@ restore_link:
 
 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
 {
-       return port < chip->info->num_internal_phys;
+       return port >= chip->info->internal_phys_offset &&
+               port < chip->info->num_internal_phys +
+                       chip->info->internal_phys_offset;
 }
 
 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)

diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index b34e96e689d5cfa05c694a151d2301eebb6b92b8..4a8b56ed1bd6cd7d5ce01e249c20ff070c152c08 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -167,6 +167,11 @@ struct mv88e6xxx_info {
 
        /* Supports PTP */
        bool ptp_support;
+
+       /* Internal PHY start index. 0 means that internal PHYs range starts at
+        * port 0, 1 means internal PHYs range starts at port 1, etc
+        */
+       unsigned int internal_phys_offset;
 };
 
 struct mv88e6xxx_atu_entry {

diff --git a/drivers/net/dsa/mv88e6xxx/global2.c b/drivers/net/dsa/mv88e6xxx/global2.c
index 79954e580c3353d07be6db632c4afb8565c6648b..8480d08e6f944e4e75db8a427c5fb026e15e0b64 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/global2.c
+++ b/drivers/net/dsa/mv88e6xxx/global2.c
@@ -1184,9 +1184,12 @@ out:
 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
                                struct mii_bus *bus)
 {
+       int phy_start = chip->info->internal_phys_offset;
+       int phy_end = chip->info->internal_phys_offset +
+                     chip->info->num_internal_phys;
        int phy, irq;
 
-       for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
+       for (phy = phy_start; phy < phy_end; phy++) {
                irq = irq_find_mapping(chip->g2_irq.domain, phy);
                if (irq < 0)
                        return irq;