#define AMD64G_CC_SHIFT_C 0
#define AMD64G_CC_SHIFT_P 2
-#define AMD64G_CC_MASK_O (1 << AMD64G_CC_SHIFT_O)
-#define AMD64G_CC_MASK_S (1 << AMD64G_CC_SHIFT_S)
-#define AMD64G_CC_MASK_Z (1 << AMD64G_CC_SHIFT_Z)
-#define AMD64G_CC_MASK_A (1 << AMD64G_CC_SHIFT_A)
-#define AMD64G_CC_MASK_C (1 << AMD64G_CC_SHIFT_C)
-#define AMD64G_CC_MASK_P (1 << AMD64G_CC_SHIFT_P)
+#define AMD64G_CC_MASK_O (1ULL << AMD64G_CC_SHIFT_O)
+#define AMD64G_CC_MASK_S (1ULL << AMD64G_CC_SHIFT_S)
+#define AMD64G_CC_MASK_Z (1ULL << AMD64G_CC_SHIFT_Z)
+#define AMD64G_CC_MASK_A (1ULL << AMD64G_CC_SHIFT_A)
+#define AMD64G_CC_MASK_C (1ULL << AMD64G_CC_SHIFT_C)
+#define AMD64G_CC_MASK_P (1ULL << AMD64G_CC_SHIFT_P)
/* FPU flag masks */
#define AMD64G_FC_SHIFT_C3 14
#define AMD64G_FC_SHIFT_C1 9
#define AMD64G_FC_SHIFT_C0 8
-#define AMD64G_FC_MASK_C3 (1 << AMD64G_FC_SHIFT_C3)
-#define AMD64G_FC_MASK_C2 (1 << AMD64G_FC_SHIFT_C2)
-#define AMD64G_FC_MASK_C1 (1 << AMD64G_FC_SHIFT_C1)
-#define AMD64G_FC_MASK_C0 (1 << AMD64G_FC_SHIFT_C0)
+#define AMD64G_FC_MASK_C3 (1ULL << AMD64G_FC_SHIFT_C3)
+#define AMD64G_FC_MASK_C2 (1ULL << AMD64G_FC_SHIFT_C2)
+#define AMD64G_FC_MASK_C1 (1ULL << AMD64G_FC_SHIFT_C1)
+#define AMD64G_FC_MASK_C0 (1ULL << AMD64G_FC_SHIFT_C0)
/* %RFLAGS thunk descriptors. A four-word thunk is used to record