ia64.c (expand_vec_perm_interleave_2): Use gen_raw_REG to create a register in testin...

	* config/ia64/ia64.c (expand_vec_perm_interleave_2): Use gen_raw_REG
	to create a register in testing mode.

From-SVN: r221140

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 809f5cfb85ae009c4d69e258385f91fbb37bac4d..b85002d1bb17683af5bbf71b7a0014b60470d58f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-03-03  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * config/ia64/ia64.c (expand_vec_perm_interleave_2): Use gen_raw_REG
+       to create a register in testing mode.
+
 2015-03-03  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
        Backport from mainline

diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 41adc4adc963aace42b3066a626dacdfda142b6f..229a0f386b4cb0f04f78307338185bab153f9fa0 100644 (file)
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -11495,7 +11495,10 @@ expand_vec_perm_interleave_2 (struct expand_vec_perm_d *d)
       gcc_assert (e < nelt);
       dfinal.perm[i] = e;
     }
-  dfinal.op0 = gen_reg_rtx (dfinal.vmode);
+  if (d->testing_p)
+    dfinal.op0 = gen_raw_REG (dfinal.vmode, LAST_VIRTUAL_REGISTER + 1);
+  else
+    dfinal.op0 = gen_reg_rtx (dfinal.vmode);
   dfinal.op1 = dfinal.op0;
   dfinal.one_operand_p = true;
   dremap.target = dfinal.op0;