]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
RISC-V: Reconcile the existing test for vrem.vx combine
authorPan Li <pan2.li@intel.com>
Sun, 8 Jun 2025 08:50:52 +0000 (16:50 +0800)
committerPan Li <pan2.li@intel.com>
Mon, 9 Jun 2025 01:32:22 +0000 (09:32 +0800)
Some existing vrem related test need some adjust for the
asm check due to cost model.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Adjust the
asm check for vrem.
* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c

index a87a6c70df1f7b3573e2dadd40afc96b95429d34..ad918a9b800a7ca521c9b47bb549d8f661de2cbd 100644 (file)
@@ -2,8 +2,8 @@
 
 #include "vrem-template.h"
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */
-/* { dg-final { scan-assembler-times {\tvrem\.vx} 3 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvrem\.vx} } } */
 /* { dg-final { scan-assembler-times {\tvremu\.vv} 5 } } */
 /* { dg-final { scan-assembler-times {\tvremu\.vx} 3 } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */
index 938169574aac5ddb83183d2dcc4c2547de433381..4e28f99e28867103731ddb04122a009de2dda528 100644 (file)
@@ -3,8 +3,8 @@
 
 #include "vrem-template.h"
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 4 } } */
-/* { dg-final { scan-assembler-times {\tvrem\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvrem\.vx} } } */
 /* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */
 /* { dg-final { scan-assembler-times {\tvremu\.vx} 4 } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */