arm: agilex5: Enable eMMC HS200 and HS400 mode support

Enable high-speed eMMC modes on Agilex5 SoC development kit for
improved storage performance.

Defconfig changes:
- Enable CONFIG_MMC_HS400_SUPPORT and CONFIG_SPL_MMC_HS400_SUPPORT

Device tree changes:
- Add mmc-hs200-1_8v and mmc-hs400-1_8v capabilities
- Add sdhci-caps-mask to mask SDHCI_CLOCK_V3_BASE_MASK bits
- Add sdhci-caps to set 200MHz base clock and 8-bit bus width
- Add PHY and controller timing configuration for HS200 mode
- Add PHY and controller timing configuration for HS400 mode

Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Acked-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
index f6848c373cd02bfa3f6f174f7a3cea124b60a883..c06781064ca85044de39ec0166a03927c15344b8 100644 (file)
--- a/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
@@ -25,11 +25,14 @@
        disable-wp;
        non-removable;
        cap-mmc-highspeed;
-
+       mmc-hs200-1_8v;
+       mmc-hs400-1_8v;
        bus-width = <8>;
        vmmc-supply = <&sd_emmc_power>;
        vqmmc-supply = <&emmc_io_1v8_reg>;
        max-frequency = <200000000>;
+       sdhci-caps = <0x00000000 0x0004c800>;   /* SDHCI_CAN_DO_8BIT */
+       sdhci-caps-mask = <0x00000000 0x0000ff00>;
 
        /* eMMC legacy mode timing configuration */
        cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
@@ -46,4 +49,26 @@
        cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>;
        cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
        cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>;
+
+       /* eMMC HS200 mode timing configuration */
+       cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>;
+       cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>;
+       cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>;
+       cdns,phy-dq-timing-delay-emmc-hs200 = <0x10000001>;
+       cdns,phy-dll-master-ctrl-emmc-hs200 = <0x4>;
+       cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>;
+       cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>;
+       cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>;
+       cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>;
+
+       /* eMMC HS400 mode timing configuration */
+       cdns,phy-dqs-timing-delay-emmc-hs400 = <0x680004>;
+       cdns,phy-gate-lpbk-ctrl-delay-emmc-hs400 = <0x81a40040>;
+       cdns,phy-dll-slave-ctrl-emmc-hs400 = <0x4d4b40>;
+       cdns,phy-dq-timing-delay-emmc-hs400 = <0x10000001>;
+       cdns,phy-dll-master-ctrl-emmc-hs400 = <0x4>;
+       cdns,ctrl-hrs09-timing-delay-emmc-hs400 = <0xf1c18000>;
+       cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs400 = <0x80000>;
+       cdns,ctrl-hrs16-slave-ctrl-emmc-hs400 = <0x11000001>;
+       cdns,ctrl-hrs07-timing-delay-emmc-hs400 = <0x90001>;
 };

diff --git a/configs/socfpga_agilex5_emmc_defconfig b/configs/socfpga_agilex5_emmc_defconfig
index 9254ab92e0c250902b3e61dd4d3fe2cf44cbe140..47d345be97c9733b2a415b4a765c4b2ff1f1e9fa 100644 (file)
--- a/configs/socfpga_agilex5_emmc_defconfig
+++ b/configs/socfpga_agilex5_emmc_defconfig
@@ -4,3 +4,5 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_emmc"
 # CONFIG_SPL_DM_REGULATOR_GPIO is not set
 # CONFIG_DM_REGULATOR_GPIO is not set
 # CONFIG_SPL_DWAPB_GPIO is not set
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y