arm64: dts: imx8q: add camera ov5640 support for imx8qm-mek and imx8qxp-mek

Add ov5640 overlay file for imx8qm-mek and imx8qxp-mek board. Camera can
connect different CSI port. So use dts overlay file to handle these
difference connect options.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index c02a1a93eafabbb5c7c6676140decda5c2a4e433..23535ed47631ca8f9db65bec5c07b6a7a7e36525 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -309,6 +309,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval-v1.2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
+
+imx8qm-mek-ov5640-csi0-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo
+dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi0.dtb
+imx8qm-mek-ov5640-csi1-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi1.dtbo
+dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi1.dtb
+imx8qm-mek-ov5640-dual-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo imx8qm-mek-ov5640-csi1.dtbo
+dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-dual.dtb
+
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
@@ -319,6 +327,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
 imx8qxp-mek-pcie-ep-dtbs += imx8qxp-mek.dtb imx-pcie0-ep.dtbo
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb
 
+imx8qxp-mek-ov5640-csi-dtbs := imx8qxp-mek.dtb imx8qxp-mek-ov5640-csi.dtbo
+dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-csi.dtb
+
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso
new file mode 100644 (file)
index 0000000..ceb63c2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
+
+&i2c_mipi_csi0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       clock-frequency = <100000>;
+       pinctrl-0 = <&pinctrl_i2c_mipi_csi0>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       ov5640_mipi_0: camera@3c {
+               compatible = "ovti,ov5640";
+               reg = <0x3c>;
+               clocks = <&xtal24m>;
+               clock-names = "xclk";
+               pinctrl-0 = <&pinctrl_mipi_csi0>;
+               pinctrl-names = "default";
+               powerdown-gpios = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
+               reset-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_LOW>;
+               AVDD-supply = <&reg_2v8>;
+               DVDD-supply = <&reg_1v5>;
+               DOVDD-supply = <&reg_1v8>;
+
+               port {
+                       ov5640_mipi_0_ep: endpoint {
+                               bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+                               data-lanes = <1 2>;
+                               remote-endpoint = <&mipi_csi0_in>;
+                       };
+               };
+       };
+};
+
+&irqsteer_csi0 {
+       status = "okay";
+};
+
+&isi {
+       status = "okay";
+};
+
+&mipi_csi_0 {
+       status = "okay";
+
+       ports {
+               port@0 {
+                       mipi_csi0_in: endpoint {
+                               data-lanes = <1 2>;
+                               remote-endpoint = <&ov5640_mipi_0_ep>;
+                       };
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso
new file mode 100644 (file)
index 0000000..9e6d33c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
+
+&i2c_mipi_csi1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       clock-frequency = <100000>;
+       pinctrl-0 = <&pinctrl_i2c_mipi_csi1>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       ov5640_mipi_1: camera@3c {
+               compatible = "ovti,ov5640";
+               reg = <0x3c>;
+               clocks = <&xtal24m>;
+               clock-names = "xclk";
+               pinctrl-0 = <&pinctrl_mipi_csi1>;
+               pinctrl-names = "default";
+               powerdown-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>;
+               reset-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_LOW>;
+               AVDD-supply = <&reg_2v8>;
+               DVDD-supply = <&reg_1v5>;
+               DOVDD-supply = <&reg_1v8>;
+
+               port {
+                       ov5640_mipi_1_ep: endpoint {
+                               bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+                               data-lanes = <1 2>;
+                               remote-endpoint = <&mipi_csi1_in>;
+                       };
+               };
+       };
+};
+
+&irqsteer_csi1 {
+       status = "okay";
+};
+
+&isi {
+       status = "okay";
+};
+
+&mipi_csi_1 {
+       status = "okay";
+
+       ports {
+               port@0 {
+                       mipi_csi1_in: endpoint {
+                               data-lanes = <1 2>;
+                               remote-endpoint = <&ov5640_mipi_1_ep>;
+                       };
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 9fa332dcacf45a148a9a0fd9993b8f0a3bd40fe6..95523c5381357b66a9d79a2c90926e6dd1b921d0 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -32,6 +32,13 @@
                reg = <0x00000000 0x80000000 0 0x40000000>;
        };
 
+       xtal24m: clock-xtal24m {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+               clock-output-names = "xtal_24MHz";
+       };
+
        reserved-memory {
                #address-cells = <2>;
                #size-cells = <2>;
@@ -221,6 +228,27 @@
                };
        };
 
+       reg_1v5: regulator-1v5 {
+               compatible = "regulator-fixed";
+               regulator-name = "1v5";
+               regulator-min-microvolt = <1500000>;
+               regulator-max-microvolt = <1500000>;
+       };
+
+       reg_1v8: regulator-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "1v8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+
+       reg_2v8: regulator-2v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "2v8";
+               regulator-min-microvolt = <2800000>;
+               regulator-max-microvolt = <2800000>;
+       };
+
        reg_usdhc2_vmmc: usdhc2-vmmc {
                compatible = "regulator-fixed";
                regulator-name = "SD1_SPWR";
@@ -885,6 +913,20 @@
                >;
        };
 
+       pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp {
+               fsl,pins = <
+                       IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL            0xc2000020
+                       IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA            0xc2000020
+               >;
+       };
+
+       pinctrl_i2c_mipi_csi1: i2c-mipi-csi1grp {
+               fsl,pins = <
+                       IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL            0xc2000020
+                       IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA            0xc2000020
+               >;
+       };
+
        pinctrl_i2c0: i2c0grp {
                fsl,pins = <
                        IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL                     0x06000021
@@ -1078,6 +1120,22 @@
                >;
        };
 
+       pinctrl_mipi_csi0: mipi-csi0grp {
+               fsl,pins = <
+                       IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27               0xC0000041
+                       IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28               0xC0000041
+                       IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT        0xC0000041
+               >;
+       };
+
+       pinctrl_mipi_csi1: mipi-csi1grp {
+               fsl,pins = <
+                       IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30               0xC0000041
+                       IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31               0xC0000041
+                       IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT        0xC0000041
+               >;
+       };
+
        pinctrl_pciea: pcieagrp {
                fsl,pins = <
                        IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28                0x04000021

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso
new file mode 100644 (file)
index 0000000..dd65ed8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
+
+&i2c_mipi_csi0 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       clock-frequency = <100000>;
+       pinctrl-0 = <&pinctrl_i2c_mipi_csi0>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       ov5640_mipi: camera@3c {
+               compatible = "ovti,ov5640";
+               reg = <0x3c>;
+               clocks = <&xtal24m>;
+               clock-names = "xclk";
+               pinctrl-0 = <&pinctrl_mipi_csi0>;
+               pinctrl-names = "default";
+               powerdown-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>;
+               reset-gpios = <&lsio_gpio3 8 GPIO_ACTIVE_LOW>;
+               AVDD-supply = <&reg_2v8>;
+               DVDD-supply = <&reg_1v5>;
+               DOVDD-supply = <&reg_1v8>;
+
+               port {
+                       ov5640_mipi_ep: endpoint {
+                               bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+                               data-lanes = <1 2>;
+                               remote-endpoint = <&mipi_csi0_in>;
+                       };
+               };
+       };
+};
+
+&irqsteer_csi0 {
+       status = "okay";
+};
+
+&isi {
+       status = "okay";
+};
+
+&mipi_csi_0 {
+       status = "okay";
+
+       ports {
+               port@0 {
+                       mipi_csi0_in: endpoint {
+                               data-lanes = <1 2>;
+                               remote-endpoint = <&ov5640_mipi_ep>;
+                       };
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 2259070f0e3a3f2428802b8c15bbfae1f6c40349..e54be7f649ffb0e48c62cd97ea5d0c4c05903050 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -129,6 +129,27 @@
                };
        };
 
+       reg_1v5: regulator-1v5 {
+               compatible = "regulator-fixed";
+               regulator-name = "1v5";
+               regulator-min-microvolt = <1500000>;
+               regulator-max-microvolt = <1500000>;
+       };
+
+       reg_1v8: regulator-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "1v8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+
+       reg_2v8: regulator-2v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "2v8";
+               regulator-min-microvolt = <2800000>;
+               regulator-max-microvolt = <2800000>;
+       };
+
        reg_pcieb: regulator-pcie {
                compatible = "regulator-fixed";
                regulator-max-microvolt = <3300000>;
@@ -846,6 +867,13 @@
                >;
        };
 
+       pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp {
+               fsl,pins = <
+                       IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL           0xc2000020
+                       IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA           0xc2000020
+               >;
+       };
+
        pinctrl_ioexp_rst: ioexprstgrp {
                fsl,pins = <
                        IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01                        0x06000021
@@ -886,6 +914,14 @@
                >;
        };
 
+       pinctrl_mipi_csi0: mipi-csi0grp {
+               fsl,pins = <
+                       IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07              0xC0000041
+                       IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08              0xC0000041
+                       IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT       0xC0000041
+               >;
+       };
+
        pinctrl_pcieb: pcieagrp {
                fsl,pins = <
                        IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00              0x06000021