phy: rockchip: samsung-hdptx: Fix coding style alignment

Handle a bunch of reported checkpatch.pl complaints:

  CHECK: Alignment should match open parenthesis

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-3-8d5f97419c0b@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 89710066d70c8421c2da2416529ce0082b92e571..3f8a7f4f5cd8d5c19134a813d6e1eaf5b7720b37 100644 (file)
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -1624,11 +1624,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
                regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
                                   LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
                                   FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
-                                  ctrl->tx_jeq_even_ctrl));
+                                             ctrl->tx_jeq_even_ctrl));
                regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
                                   LN_TX_JEQ_ODD_CTRL_RBR_MASK,
                                   FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
-                                  ctrl->tx_jeq_odd_ctrl));
+                                             ctrl->tx_jeq_odd_ctrl));
                regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
                                   LN_TX_SER_40BIT_EN_RBR_MASK,
                                   FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
@@ -1638,11 +1638,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
                regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
                                   LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
                                   FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
-                                  ctrl->tx_jeq_even_ctrl));
+                                             ctrl->tx_jeq_even_ctrl));
                regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
                                   LN_TX_JEQ_ODD_CTRL_HBR_MASK,
                                   FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
-                                  ctrl->tx_jeq_odd_ctrl));
+                                             ctrl->tx_jeq_odd_ctrl));
                regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
                                   LN_TX_SER_40BIT_EN_HBR_MASK,
                                   FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
@@ -1653,11 +1653,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
                regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
                                   LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
                                   FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
-                                  ctrl->tx_jeq_even_ctrl));
+                                             ctrl->tx_jeq_even_ctrl));
                regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
                                   LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
                                   FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
-                                  ctrl->tx_jeq_odd_ctrl));
+                                             ctrl->tx_jeq_odd_ctrl));
                regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
                                   LN_TX_SER_40BIT_EN_HBR2_MASK,
                                   FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));