ret = reset_control_assert(rstc);
if (ret)
- dev_err(dev, "Failed to de-assert reset!");
+ dev_err(dev, "Failed to de-assert reset!\n");
ret = pm_runtime_put_sync(dev);
if (ret < 0)
- dev_err(dev, "Failed to runtime suspend!");
+ dev_err(dev, "Failed to runtime suspend!\n");
of_clk_del_provider(dev->of_node);
}
}
if (IS_ERR(clk))
- dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
+ dev_err(dev, "Cannot get %s clock %u: %ld\n", type, clkidx,
PTR_ERR(clk));
else
dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
!(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
if (ret) {
- dev_err(priv->dev, "failed to release pll5 lock");
+ dev_err(priv->dev, "failed to release pll5 lock\n");
return ret;
}
ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
if (ret) {
- dev_err(priv->dev, "failed to lock pll5");
+ dev_err(priv->dev, "failed to lock pll5\n");
return ret;
}
}
if (IS_ERR(clk))
- dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
+ dev_err(dev, "Cannot get %s clock %u: %ld\n", type, clkidx,
PTR_ERR(clk));
else
dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
val, !(val & CPG_PLL_MON_LOCK),
100, 2000);
if (ret) {
- dev_err(priv->dev, "Failed to put PLLDSI into standby mode");
+ dev_err(priv->dev, "Failed to put PLLDSI into standby mode\n");
return ret;
}
val, (val & CPG_PLL_MON_LOCK),
100, 2000);
if (ret) {
- dev_err(priv->dev, "Failed to put PLLDSI into normal mode");
+ dev_err(priv->dev, "Failed to put PLLDSI into normal mode\n");
return ret;
}
}
if (IS_ERR(clk))
- dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
+ dev_err(dev, "Cannot get %s clock %u: %ld\n", type, clkidx,
PTR_ERR(clk));
else
dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",