mips: fix mips32r6 and mips64r6 compilation issue

Add missing variable declarations.
Modify local_sys_write_stderr to use movn if available, and use
seleqz/selnez instructions otherwise.

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index eb437ec084fff3089e00432d75df9751bf6b852a..6e91329f2f3fcefd7158afd10acb60bf9499ce1a 100755 (executable)
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -20241,6 +20241,7 @@ static UInt disInstr_MIPS_WRK_00(UInt cins, const VexArchInfo* archinfo,
 #elif defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 6))
 
       case 0x08: { /* BEQZALC, BEQC, BOVC */
+         IRTemp t1, t2, t3, t4;
          if (rs == 0) { /* BEQZALC */
             DIP("beqzalc r%u, %u", rt, imm);
 

diff --git a/coregrind/m_debuglog.c b/coregrind/m_debuglog.c
index 456a711297f87ad4ba0f512d3c1e68e4951acb3c..289f27592e8f7e4f899ce7520bb42749aad079c0 100644 (file)
--- a/coregrind/m_debuglog.c
+++ b/coregrind/m_debuglog.c
@@ -452,7 +452,13 @@ static UInt local_sys_write_stderr ( const HChar* buf, Int n )
    __asm__ volatile (
       "syscall            \n\t"
       "addiu   $4, $0, -1 \n\t"
+      #if ((defined(__mips_isa_rev) && __mips_isa_rev >= 6))
+      "selnez  $4, $4, $7 \n\t"
+      "seleqz  $2, $2, $7 \n\t"
+      "or      $2, $2, $4 \n\t"
+      #else
       "movn    $2, $4, $7 \n\t"
+      #endif
      : "+d" (v0), "+d" (a0), "+d" (a1), "+d" (a2)
      :
      : "$1", "$3", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",