arm64: dts: renesas: r9a09g077: Add DMAC support

The Renesas RZ/T2H (R9A09G077) SoC has three instances of the DMAC IP.

Add support for them.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251205151254.2970669-6-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 63de8271f47c0133cf38190f5e4b20888f735e89..2db5f5e94f7cab47a1646039baf3080df5d56e98 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -342,6 +342,96 @@
                        status = "disabled";
                };
 
+               dmac0: dma-controller@800c0000 {
+                       compatible = "renesas,r9a09g077-dmac";
+                       reg = <0 0x800c0000 0 0x1000>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15";
+                       clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>;
+                       power-domains = <&cpg>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       renesas,icu = <&icu 0>;
+               };
+
+               dmac1: dma-controller@800c1000 {
+                       compatible = "renesas,r9a09g077-dmac";
+                       reg = <0 0x800c1000 0 0x1000>;
+                       interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15";
+                       clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>;
+                       power-domains = <&cpg>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       renesas,icu = <&icu 1>;
+               };
+
+               dmac2: dma-controller@800c2000 {
+                       compatible = "renesas,r9a09g077-dmac";
+                       reg = <0 0x800c2000 0 0x1000>;
+                       interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15";
+                       clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>;
+                       power-domains = <&cpg>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       renesas,icu = <&icu 2>;
+               };
+
                gmac0: ethernet@80100000 {
                        compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20";
                        reg = <0 0x80100000 0 0x10000>;