/* Instructions shared between ARMv8-A and ARMv8-M. */
static const arm_feature_set arm_ext_atomics =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
-/* DSP instructions Tag_DSP_extension refers to. */
-static const arm_feature_set arm_ext_dsp =
- ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
static const arm_feature_set arm_arch_any = ARM_ANY;
static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1, -1);
ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
- ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
- ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
- ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
char profile;
int virt_sec = 0;
int fp16_optional = 0;
- arm_feature_set arm_arch = ARM_ARCH_NONE;
arm_feature_set flags;
arm_feature_set tmp;
arm_feature_set arm_arch_v8m_base = ARM_ARCH_V8M_BASE;
if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
{
arch = p->val;
- arm_arch = p->flags;
ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
}
}
&& !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
&& ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
&& ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
- {
- arch = TAG_CPU_ARCH_V7E_M;
- arm_arch = (arm_feature_set) ARM_ARCH_V7EM;
- }
+ arch = TAG_CPU_ARCH_V7E_M;
ARM_CLEAR_FEATURE (tmp, flags, arm_arch_v8m_base);
if (arch == TAG_CPU_ARCH_V8M_BASE && ARM_CPU_HAS_FEATURE (tmp, arm_arch_any))
- {
- arch = TAG_CPU_ARCH_V8M_MAIN;
- arm_arch = (arm_feature_set) ARM_ARCH_V8M_MAIN;
- }
+ arch = TAG_CPU_ARCH_V8M_MAIN;
/* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
coming from ARMv8-A. However, since ARMv8-A has more instructions than
ARMv8-M, -march=all must be detected as ARMv8-A. */
if (arch == TAG_CPU_ARCH_V8M_MAIN
&& ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
- {
- arch = TAG_CPU_ARCH_V8;
- arm_arch = (arm_feature_set) ARM_ARCH_V8A;
- }
+ arch = TAG_CPU_ARCH_V8;
/* Tag_CPU_name. */
if (selected_cpu_name[0])
if (profile != '\0')
aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
- /* Tag_DSP_extension. */
- if (ARM_CPU_HAS_FEATURE (flags, arm_ext_dsp))
- {
- arm_feature_set ext;
-
- /* DSP instructions not in architecture. */
- ARM_CLEAR_FEATURE (ext, flags, arm_arch);
- if (ARM_CPU_HAS_FEATURE (ext, arm_ext_dsp))
- aeabi_set_attribute_int (Tag_DSP_extension, 1);
- }
-
/* Tag_ARM_ISA_use. */
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
|| arch == 0)
T (Tag_conformance),
T (Tag_T2EE_use),
T (Tag_Virtualization_use),
- T (Tag_DSP_extension),
/* We deliberately do not include Tag_MPextension_use_legacy. */
#undef T
};
+++ /dev/null
-#name: ARM V8-M mainline with DSP instructions (base)
-#source: archv8m.s
-#as: -march=armv8-m.main+dsp
-#objdump: -dr --prefix-addresses --show-raw-insn
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+.* <[^>]*> 47a0 blx r4
-0+.* <[^>]*> 47c8 blx r9
-0+.* <[^>]*> 4720 bx r4
-0+.* <[^>]*> 4748 bx r9
-0+.* <[^>]*> e841 f000 tt r0, r1
-0+.* <[^>]*> e849 f800 tt r8, r9
-0+.* <[^>]*> e841 f040 ttt r0, r1
-0+.* <[^>]*> e849 f840 ttt r8, r9
-0+.* <[^>]*> f24f 1023 movw r0, #61731 ; 0xf123
-0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1023 movt r0, #61731 ; 0xf123
-0+.* <[^>]*> f2cf 1823 movt r8, #61731 ; 0xf123
-0+.* <[^>]*> b154 cbz r4, 0+.* <[^>]*>
-0+.* <[^>]*> b94c cbnz r4, 0+.* <[^>]*>
-0+.* <[^>]*> f000 b808 b.w 0+.* <[^>]*>
-0+.* <[^>]*> fb91 f0f2 sdiv r0, r1, r2
-0+.* <[^>]*> fb99 f8fa sdiv r8, r9, sl
-0+.* <[^>]*> fbb1 f0f2 udiv r0, r1, r2
-0+.* <[^>]*> fbb9 f8fa udiv r8, r9, sl
-0+.* <[^>]*> 4408 add r0, r1
-0+.* <[^>]*> f3bf 8f2f clrex
-0+.* <[^>]*> e851 0f01 ldrex r0, \[r1, #4\]
-0+.* <[^>]*> e8d1 0f4f ldrexb r0, \[r1\]
-0+.* <[^>]*> e8d1 0f5f ldrexh r0, \[r1\]
-0+.* <[^>]*> e842 1001 strex r0, r1, \[r2, #4\]
-0+.* <[^>]*> e8c2 1f40 strexb r0, r1, \[r2\]
-0+.* <[^>]*> e8c2 1f50 strexh r0, r1, \[r2\]
-0+.* <[^>]*> e8d1 0faf lda r0, \[r1\]
-0+.* <[^>]*> e8d1 0f8f ldab r0, \[r1\]
-0+.* <[^>]*> e8d1 0f9f ldah r0, \[r1\]
-0+.* <[^>]*> e8c1 0faf stl r0, \[r1\]
-0+.* <[^>]*> e8c1 0f8f stlb r0, \[r1\]
-0+.* <[^>]*> e8c1 0f9f stlh r0, \[r1\]
-0+.* <[^>]*> e8d1 0fef ldaex r0, \[r1\]
-0+.* <[^>]*> e8d1 0fcf ldaexb r0, \[r1\]
-0+.* <[^>]*> e8d1 0fdf ldaexh r0, \[r1\]
-0+.* <[^>]*> e8c2 1fe0 stlex r0, r1, \[r2\]
-0+.* <[^>]*> e8c2 1fc0 stlexb r0, r1, \[r2\]
-0+.* <[^>]*> e8c2 1fd0 stlexh r0, r1, \[r2\]
+++ /dev/null
-#name: ARM V8-M mainline with DSP instructions (extension)
-#source: arch7em.s
-#as: -march=armv8-m.main+dsp
-#objdump: -dr --prefix-addresses --show-raw-insn
-#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0[0-9a-f]+ <[^>]+> eac0 0000 pkhbt r0, r0, r0
-0[0-9a-f]+ <[^>]+> eac0 0900 pkhbt r9, r0, r0
-0[0-9a-f]+ <[^>]+> eac9 0000 pkhbt r0, r9, r0
-0[0-9a-f]+ <[^>]+> eac0 0009 pkhbt r0, r0, r9
-0[0-9a-f]+ <[^>]+> eac0 5000 pkhbt r0, r0, r0, lsl #20
-0[0-9a-f]+ <[^>]+> eac0 00c0 pkhbt r0, r0, r0, lsl #3
-0[0-9a-f]+ <[^>]+> eac3 0102 pkhbt r1, r3, r2
-0[0-9a-f]+ <[^>]+> eac2 4163 pkhtb r1, r2, r3, asr #17
-0[0-9a-f]+ <[^>]+> fa83 f182 qadd r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa92 f113 qadd16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa82 f113 qadd8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f113 qasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f113 qasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa83 f192 qdadd r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa83 f1b2 qdsub r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa83 f1a2 qsub r1, r2, r3
-0[0-9a-f]+ <[^>]+> fad2 f113 qsub16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fac2 f113 qsub8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f113 qsax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f113 qsax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa92 f103 sadd16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa82 f103 sadd8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f103 sasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f103 sasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> fad2 f103 ssub16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fac2 f103 ssub8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f103 ssax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f103 ssax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa92 f123 shadd16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa82 f123 shadd8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f123 shasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f123 shasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> fad2 f123 shsub16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fac2 f123 shsub8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f123 shsax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f123 shsax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa92 f143 uadd16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa82 f143 uadd8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f143 uasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f143 uasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> fad2 f143 usub16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fac2 f143 usub8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f143 usax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f143 usax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa92 f163 uhadd16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa82 f163 uhadd8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f163 uhasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f163 uhasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> fad2 f163 uhsub16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fac2 f163 uhsub8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f163 uhsax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f163 uhsax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa92 f153 uqadd16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa82 f153 uqadd8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f153 uqasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f153 uqasx r1, r2, r3
-0[0-9a-f]+ <[^>]+> fad2 f153 uqsub16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fac2 f153 uqsub8 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f153 uqsax r1, r2, r3
-0[0-9a-f]+ <[^>]+> fae2 f153 uqsax r1, r2, r3
-0[0-9a-f]+ <[^>]+> faa2 f183 sel r1, r2, r3
-0[0-9a-f]+ <[^>]+> fb10 0000 smlabb r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb10 0900 smlabb r9, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb19 0000 smlabb r0, r9, r0, r0
-0[0-9a-f]+ <[^>]+> fb10 0009 smlabb r0, r0, r9, r0
-0[0-9a-f]+ <[^>]+> fb10 9000 smlabb r0, r0, r0, r9
-0[0-9a-f]+ <[^>]+> fb10 0020 smlatb r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb10 0010 smlabt r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb10 0030 smlatt r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb30 0000 smlawb r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb30 0010 smlawt r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb20 0000 smlad r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb20 0010 smladx r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb40 0000 smlsd r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb40 0010 smlsdx r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb50 0000 smmla r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb50 0010 smmlar r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb60 0000 smmls r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb60 0010 smmlsr r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb70 0000 usada8 r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbc0 0080 smlalbb r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbc0 9080 smlalbb r9, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbc0 0980 smlalbb r0, r9, r0, r0
-0[0-9a-f]+ <[^>]+> fbc9 0080 smlalbb r0, r0, r9, r0
-0[0-9a-f]+ <[^>]+> fbc0 0089 smlalbb r0, r0, r0, r9
-0[0-9a-f]+ <[^>]+> fbc0 00a0 smlaltb r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbc0 0090 smlalbt r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbc0 00b0 smlaltt r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbc0 00c0 smlald r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbc0 00d0 smlaldx r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbd0 00c0 smlsld r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbd0 00d0 smlsldx r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fbe0 0060 umaal r0, r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb10 f000 smulbb r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb10 f900 smulbb r9, r0, r0
-0[0-9a-f]+ <[^>]+> fb19 f000 smulbb r0, r9, r0
-0[0-9a-f]+ <[^>]+> fb10 f009 smulbb r0, r0, r9
-0[0-9a-f]+ <[^>]+> fb10 f020 smultb r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb10 f010 smulbt r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb10 f030 smultt r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb30 f000 smulwb r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb30 f010 smulwt r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb50 f000 smmul r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb50 f010 smmulr r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb20 f000 smuad r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb20 f010 smuadx r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb40 f000 smusd r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb40 f010 smusdx r0, r0, r0
-0[0-9a-f]+ <[^>]+> fb70 f000 usad8 r0, r0, r0
-0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #1, r0
-0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #1, r0
-0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #10, r0
-0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #1, r9
-0[0-9a-f]+ <[^>]+> f3a0 0000 usat16 r0, #0, r0
-0[0-9a-f]+ <[^>]+> f3a0 0900 usat16 r9, #0, r0
-0[0-9a-f]+ <[^>]+> f3a0 0009 usat16 r0, #9, r0
-0[0-9a-f]+ <[^>]+> f3a9 0000 usat16 r0, #0, r9
-0[0-9a-f]+ <[^>]+> fa2f f182 sxtb16 r1, r2
-0[0-9a-f]+ <[^>]+> fa2f f889 sxtb16 r8, r9
-0[0-9a-f]+ <[^>]+> fa3f f182 uxtb16 r1, r2
-0[0-9a-f]+ <[^>]+> fa3f f889 uxtb16 r8, r9
-0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0
-0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0
-0[0-9a-f]+ <[^>]+> fa40 f990 sxtab r9, r0, r0, ror #8
-0[0-9a-f]+ <[^>]+> fa49 f0a0 sxtab r0, r9, r0, ror #16
-0[0-9a-f]+ <[^>]+> fa40 f0b9 sxtab r0, r0, r9, ror #24
-0[0-9a-f]+ <[^>]+> fa22 f183 sxtab16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa02 f183 sxtah r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa52 f183 uxtab r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa32 f183 uxtab16 r1, r2, r3
-0[0-9a-f]+ <[^>]+> fa12 f183 uxtah r1, r2, r3