clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe

Video PLLs on SM8450/SM8475 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management, PLL
configuration and enable critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-7-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c
index 2e11dcffb6646d47b298c27ef68635a465dd728e..d53182f001262324d8f54b0c6a5e73541eb32190 100644 (file)
--- a/drivers/clk/qcom/videocc-sm8450.c
+++ b/drivers/clk/qcom/videocc-sm8450.c
@@ -7,7 +7,6 @@
 #include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 
 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
@@ -63,6 +62,7 @@ static const struct alpha_pll_config sm8475_video_cc_pll0_config = {
 
 static struct clk_alpha_pll video_cc_pll0 = {
        .offset = 0x0,
+       .config = &video_cc_pll0_config,
        .vco_table = lucid_evo_vco,
        .num_vco = ARRAY_SIZE(lucid_evo_vco),
        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@@ -106,6 +106,7 @@ static const struct alpha_pll_config sm8475_video_cc_pll1_config = {
 
 static struct clk_alpha_pll video_cc_pll1 = {
        .offset = 0x1000,
+       .config = &video_cc_pll1_config,
        .vco_table = lucid_evo_vco,
        .num_vco = ARRAY_SIZE(lucid_evo_vco),
        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@@ -407,6 +408,17 @@ static const struct qcom_reset_map video_cc_sm8450_resets[] = {
        [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x808c, .bit = 2, .udelay = 1000 },
 };
 
+static struct clk_alpha_pll *video_cc_sm8450_plls[] = {
+       &video_cc_pll0,
+       &video_cc_pll1,
+};
+
+static u32 video_cc_sm8450_critical_cbcrs[] = {
+       0x80e4, /* VIDEO_CC_AHB_CLK */
+       0x8114, /* VIDEO_CC_XO_CLK */
+       0x8130, /* VIDEO_CC_SLEEP_CLK */
+};
+
 static const struct regmap_config video_cc_sm8450_regmap_config = {
        .reg_bits = 32,
        .reg_stride = 4,
@@ -415,6 +427,13 @@ static const struct regmap_config video_cc_sm8450_regmap_config = {
        .fast_io = true,
 };
 
+static struct qcom_cc_driver_data video_cc_sm8450_driver_data = {
+       .alpha_plls = video_cc_sm8450_plls,
+       .num_alpha_plls = ARRAY_SIZE(video_cc_sm8450_plls),
+       .clk_cbcrs = video_cc_sm8450_critical_cbcrs,
+       .num_clk_cbcrs = ARRAY_SIZE(video_cc_sm8450_critical_cbcrs),
+};
+
 static const struct qcom_cc_desc video_cc_sm8450_desc = {
        .config = &video_cc_sm8450_regmap_config,
        .clks = video_cc_sm8450_clocks,
@@ -423,6 +442,8 @@ static const struct qcom_cc_desc video_cc_sm8450_desc = {
        .num_resets = ARRAY_SIZE(video_cc_sm8450_resets),
        .gdscs = video_cc_sm8450_gdscs,
        .num_gdscs = ARRAY_SIZE(video_cc_sm8450_gdscs),
+       .use_rpm = true,
+       .driver_data = &video_cc_sm8450_driver_data,
 };
 
 static const struct of_device_id video_cc_sm8450_match_table[] = {
@@ -434,23 +455,6 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table);
 
 static int video_cc_sm8450_probe(struct platform_device *pdev)
 {
-       struct regmap *regmap;
-       int ret;
-
-       ret = devm_pm_runtime_enable(&pdev->dev);
-       if (ret)
-               return ret;
-
-       ret = pm_runtime_resume_and_get(&pdev->dev);
-       if (ret)
-               return ret;
-
-       regmap = qcom_cc_map(pdev, &video_cc_sm8450_desc);
-       if (IS_ERR(regmap)) {
-               pm_runtime_put(&pdev->dev);
-               return PTR_ERR(regmap);
-       }
-
        if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) {
                /* Update VideoCC PLL0 */
                video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
@@ -458,23 +462,11 @@ static int video_cc_sm8450_probe(struct platform_device *pdev)
                /* Update VideoCC PLL1 */
                video_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
 
-               clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &sm8475_video_cc_pll0_config);
-               clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &sm8475_video_cc_pll1_config);
-       } else {
-               clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
-               clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
+               video_cc_pll0.config = &sm8475_video_cc_pll0_config;
+               video_cc_pll1.config = &sm8475_video_cc_pll1_config;
        }
 
-       /* Keep some clocks always-on */
-       qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */
-       qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */
-       qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */
-
-       ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8450_desc, regmap);
-
-       pm_runtime_put(&pdev->dev);
-
-       return ret;
+       return qcom_cc_probe(pdev, &video_cc_sm8450_desc);
 }
 
 static struct platform_driver video_cc_sm8450_driver = {