Add (unused) pattern for generating rotate insns, as an example.

git-svn-id: svn://svn.valgrind.org/vex/trunk@190

diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c
index 5902f73bc6d4e86287d7a0c4fcc1a261ff89ccda..9cf821ae8c77c63a8dcb0ccabd5ce822c186e7a8 100644 (file)
--- a/VEX/priv/host-x86/isel.c
+++ b/VEX/priv/host-x86/isel.c
@@ -294,6 +294,22 @@ static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
       X86AluOp   aluOp;
       X86ShiftOp shOp;
 
+#if 0
+      { DECLARE_PATTERN(p_rol32);
+        DEFINE_PATTERN(p_rol32,
+           binop(Iop_Or32,
+                 binop(Iop_Shl32,bind(0),bind(1)),
+                 binop(Iop_Shr32,
+                       bind(2),
+                       binop(Iop_Sub8,IRConst_U8(32),bind(3)))));
+        if (matchIRExpr(&mi,p_rol32,e)
+            && eqIRExpr(mi.bindee[0], mi.bindee[2])
+            && eqIRExpr(mi.bindee[1], mi.bindee[3])) {
+           /* emit roll */
+        }
+      }
+#endif
+
       /* Is it an addition or logical style op? */
       switch (e->Iex.Binop.op) {
          case Iop_Add8: case Iop_Add16: case Iop_Add32: