x86/mce: Break up __mcheck_cpu_apply_quirks()

Split each vendor specific part into its own helper function.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Sohil Mehta <sohil.mehta@intel.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Tested-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20241212140103.66964-5-qiuxu.zhuo@intel.com

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index ce6fe5e208058c8291c14b532a74c033ae34ec43..3855ec2ed0e038edef9f70d800b700f834a8966e 100644 (file)
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1910,101 +1910,117 @@ static void __mcheck_cpu_check_banks(void)
        }
 }
 
-/* Add per CPU specific workarounds here */
-static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
+static void apply_quirks_amd(struct cpuinfo_x86 *c)
 {
        struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
-       struct mca_config *cfg = &mca_cfg;
-
-       if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
-               pr_info("unknown CPU type - not enabling MCE support\n");
-               return false;
-       }
 
        /* This should be disabled by the BIOS, but isn't always */
-       if (c->x86_vendor == X86_VENDOR_AMD) {
-               if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
-                       /*
-                        * disable GART TBL walk error reporting, which
-                        * trips off incorrectly with the IOMMU & 3ware
-                        * & Cerberus:
-                        */
-                       clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
-               }
-               if (c->x86 < 0x11 && cfg->bootlog < 0) {
-                       /*
-                        * Lots of broken BIOS around that don't clear them
-                        * by default and leave crap in there. Don't log:
-                        */
-                       cfg->bootlog = 0;
-               }
+       if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
                /*
-                * Various K7s with broken bank 0 around. Always disable
-                * by default.
+                * disable GART TBL walk error reporting, which
+                * trips off incorrectly with the IOMMU & 3ware
+                * & Cerberus:
                 */
-               if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
-                       mce_banks[0].ctl = 0;
+               clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
+       }
 
+       if (c->x86 < 0x11 && mca_cfg.bootlog < 0) {
                /*
-                * overflow_recov is supported for F15h Models 00h-0fh
-                * even though we don't have a CPUID bit for it.
+                * Lots of broken BIOS around that don't clear them
+                * by default and leave crap in there. Don't log:
                 */
-               if (c->x86 == 0x15 && c->x86_model <= 0xf)
-                       mce_flags.overflow_recov = 1;
+               mca_cfg.bootlog = 0;
+       }
 
-               if (c->x86 >= 0x17 && c->x86 <= 0x1A)
-                       mce_flags.zen_ifu_quirk = 1;
+       /*
+        * Various K7s with broken bank 0 around. Always disable
+        * by default.
+        */
+       if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
+               mce_banks[0].ctl = 0;
 
-       }
+       /*
+        * overflow_recov is supported for F15h Models 00h-0fh
+        * even though we don't have a CPUID bit for it.
+        */
+       if (c->x86 == 0x15 && c->x86_model <= 0xf)
+               mce_flags.overflow_recov = 1;
 
-       if (c->x86_vendor == X86_VENDOR_INTEL) {
-               /*
-                * SDM documents that on family 6 bank 0 should not be written
-                * because it aliases to another special BIOS controlled
-                * register.
-                * But it's not aliased anymore on model 0x1a+
-                * Don't ignore bank 0 completely because there could be a
-                * valid event later, merely don't write CTL0.
-                */
+       if (c->x86 >= 0x17 && c->x86 <= 0x1A)
+               mce_flags.zen_ifu_quirk = 1;
+}
 
-               if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
-                       mce_banks[0].init = false;
+static void apply_quirks_intel(struct cpuinfo_x86 *c)
+{
+       struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
 
-               /*
-                * All newer Intel systems support MCE broadcasting. Enable
-                * synchronization with a one second timeout.
-                */
-               if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
-                       cfg->monarch_timeout < 0)
-                       cfg->monarch_timeout = USEC_PER_SEC;
+       /*
+        * SDM documents that on family 6 bank 0 should not be written
+        * because it aliases to another special BIOS controlled
+        * register.
+        * But it's not aliased anymore on model 0x1a+
+        * Don't ignore bank 0 completely because there could be a
+        * valid event later, merely don't write CTL0.
+        */
+       if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
+               mce_banks[0].init = false;
 
-               /*
-                * There are also broken BIOSes on some Pentium M and
-                * earlier systems:
-                */
-               if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
-                       cfg->bootlog = 0;
+       /*
+        * All newer Intel systems support MCE broadcasting. Enable
+        * synchronization with a one second timeout.
+        */
+       if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
+           mca_cfg.monarch_timeout < 0)
+               mca_cfg.monarch_timeout = USEC_PER_SEC;
+
+       /*
+        * There are also broken BIOSes on some Pentium M and
+        * earlier systems:
+        */
+       if (c->x86 == 6 && c->x86_model <= 13 && mca_cfg.bootlog < 0)
+               mca_cfg.bootlog = 0;
 
-               if (c->x86_vfm == INTEL_SANDYBRIDGE_X)
-                       mce_flags.snb_ifu_quirk = 1;
+       if (c->x86_vfm == INTEL_SANDYBRIDGE_X)
+               mce_flags.snb_ifu_quirk = 1;
 
-               /*
-                * Skylake, Cascacde Lake and Cooper Lake require a quirk on
-                * rep movs.
-                */
-               if (c->x86_vfm == INTEL_SKYLAKE_X)
-                       mce_flags.skx_repmov_quirk = 1;
+       /*
+        * Skylake, Cascacde Lake and Cooper Lake require a quirk on
+        * rep movs.
+        */
+       if (c->x86_vfm == INTEL_SKYLAKE_X)
+               mce_flags.skx_repmov_quirk = 1;
+}
+
+static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c)
+{
+       /*
+        * All newer Zhaoxin CPUs support MCE broadcasting. Enable
+        * synchronization with a one second timeout.
+        */
+       if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
+               if (mca_cfg.monarch_timeout < 0)
+                       mca_cfg.monarch_timeout = USEC_PER_SEC;
        }
+}
 
-       if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
-               /*
-                * All newer Zhaoxin CPUs support MCE broadcasting. Enable
-                * synchronization with a one second timeout.
-                */
-               if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
-                       if (cfg->monarch_timeout < 0)
-                               cfg->monarch_timeout = USEC_PER_SEC;
-               }
+/* Add per CPU specific workarounds here */
+static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
+{
+       struct mca_config *cfg = &mca_cfg;
+
+       switch (c->x86_vendor) {
+       case X86_VENDOR_UNKNOWN:
+               pr_info("unknown CPU type - not enabling MCE support\n");
+               return false;
+       case X86_VENDOR_AMD:
+               apply_quirks_amd(c);
+               break;
+       case X86_VENDOR_INTEL:
+               apply_quirks_intel(c);
+               break;
+       case X86_VENDOR_ZHAOXIN:
+               apply_quirks_zhaoxin(c);
+               break;
        }
 
        if (cfg->monarch_timeout < 0)