The AER driver includes significant logic for handling CXL protocol errors.
The AER driver will be updated in the future to separate the AER and CXL
logic.
Rename the is_internal_error() function to is_aer_internal_error() as it
gives a more precise indication of the purpose. Make
is_aer_internal_error() non-static to allow for the 2 different CXL
topology error model implementations (RCH and VH) to share this helper.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Link: https://patch.msgid.link/20260114182055.46029-11-terry.bowman@amd.com
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
return true;
}
-static bool is_internal_error(struct aer_err_info *info)
+bool is_aer_internal_error(struct aer_err_info *info)
{
if (info->severity == AER_CORRECTABLE)
return info->status & PCI_ERR_COR_INTERNAL;
* device driver.
*/
if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC &&
- is_internal_error(info))
+ is_aer_internal_error(info))
pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
}
#endif /* !CONFIG_PCIE_PME */
struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
+
+struct aer_err_info;
+
+#ifdef CONFIG_PCIEAER_CXL
+bool is_aer_internal_error(struct aer_err_info *info);
+#else
+static inline bool is_aer_internal_error(struct aer_err_info *info) { return false; }
+#endif /* CONFIG_PCIEAER_CXL */
+
#endif /* _PORTDRV_H_ */