drm/edid: add a quirk for two LG monitors to get them to work on 10bpc

[ Upstream commit aa193f7eff8ff753577351140b8af13b76cdc7c2 ]

The LG 27GP950 and LG 27GN950 have visible display corruption when
trying to use 10bpc modes. So, to fix this, cap their maximum DSC
target bitrate to 15bpp.

Suggested-by: Roman Li <roman.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index eaa819381281be2f41f47e1c717cc79322e3db04..fefcfac999d993dea087b8b4af3612c13197c5a3 100644 (file)
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -87,6 +87,8 @@ static int oui(u8 first, u8 second, u8 third)
 #define EDID_QUIRK_FORCE_10BPC                 (1 << 11)
 /* Non desktop display (i.e. HMD) */
 #define EDID_QUIRK_NON_DESKTOP                 (1 << 12)
+/* Cap the DSC target bitrate to 15bpp */
+#define EDID_QUIRK_CAP_DSC_15BPP               (1 << 13)
 
 #define MICROSOFT_IEEE_OUI     0xca125c
 
@@ -147,6 +149,12 @@ static const struct edid_quirk {
        EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
                                       EDID_QUIRK_DETAILED_IN_CM),
 
+       /* LG 27GP950 */
+       EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
+
+       /* LG 27GN950 */
+       EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
+
        /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
        EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
 
@@ -6116,6 +6124,7 @@ static void drm_reset_display_info(struct drm_connector *connector)
 
        info->mso_stream_count = 0;
        info->mso_pixel_overlap = 0;
+       info->max_dsc_bpp = 0;
 }
 
 static u32 update_display_info(struct drm_connector *connector,
@@ -6202,6 +6211,9 @@ out:
                info->non_desktop = true;
        }
 
+       if (quirks & EDID_QUIRK_CAP_DSC_15BPP)
+               info->max_dsc_bpp = 15;
+
        return quirks;
 }
 

diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 7df7876b2ad5634fe373d2ef6aabe245a57ab26d..d9879fc9ceb17684b2d48a0c51322e4de34d5f07 100644 (file)
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -635,6 +635,12 @@ struct drm_display_info {
         * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
         */
        u8 mso_pixel_overlap;
+
+       /**
+        * @max_dsc_bpp: Maximum DSC target bitrate, if it is set to 0 the
+        * monitor's default value is used instead.
+        */
+       u32 max_dsc_bpp;
 };
 
 int drm_display_info_set_bus_formats(struct drm_display_info *info,