dt-bindings: clock: google,gs101-clock: Add DPU clock management unit

Add dt schema documentation and clock IDs for the Display Process Unit
(DPU) clock management unit (CMU). This CMU feeds IPs such as image scaler,
enhancer and compressor.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20260113-dpu-clocks-v3-2-cb85424f2c72@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
index 82639863b1a4a5c49a0833221d98f2ebd9369e1a..6193c87511fa4fb256de8024c2d3ea235e8736a1 100644 (file)
--- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@ -29,6 +29,7 @@ properties:
     enum:
       - google,gs101-cmu-top
       - google,gs101-cmu-apm
+      - google,gs101-cmu-dpu
       - google,gs101-cmu-hsi0
       - google,gs101-cmu-hsi2
       - google,gs101-cmu-misc
@@ -77,6 +78,24 @@ allOf:
           items:
             - const: oscclk
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-cmu-dpu
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (24.576 MHz)
+            - description: DPU bus clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+
   - if:
       properties:
         compatible:

diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
index 442f9e9037dc33198a1cee20af62fc70bbd96605..7a14dcb9f17b1e95d792b0c29fc6b8bfdc78213d 100644 (file)
--- a/include/dt-bindings/clock/google,gs101.h
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -313,6 +313,42 @@
 #define CLK_APM_PLL_DIV4_APM                           70
 #define CLK_APM_PLL_DIV16_APM                          71
 
+/* CMU_DPU */
+#define CLK_MOUT_DPU_BUS_USER                          1
+#define CLK_DOUT_DPU_BUSP                              2
+#define CLK_GOUT_DPU_PCLK                              3
+#define CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK                        4
+#define CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM              5
+#define CLK_GOUT_DPU_DPUF_ACLK_DMA                     6
+#define CLK_GOUT_DPU_DPUF_ACLK_DPP                     7
+#define CLK_GOUT_DPU_D_TZPC_DPU_PCLK                   8
+#define CLK_GOUT_DPU_GPC_DPU_PCLK                      9
+#define CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK               10
+#define CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK              11
+#define CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK              12
+#define CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK              13
+#define CLK_GOUT_DPU_PPMU_DPUD0_ACLK                   14
+#define CLK_GOUT_DPU_PPMU_DPUD0_PCLK                   15
+#define CLK_GOUT_DPU_PPMU_DPUD1_ACLK                   16
+#define CLK_GOUT_DPU_PPMU_DPUD1_PCLK                   17
+#define CLK_GOUT_DPU_PPMU_DPUD2_ACLK                   18
+#define CLK_GOUT_DPU_PPMU_DPUD2_PCLK                   19
+#define CLK_GOUT_DPU_CLK_DPU_BUSD_CLK                  20
+#define CLK_GOUT_DPU_CLK_DPU_BUSP_CLK                  21
+#define CLK_GOUT_DPU_SSMT_DPU0_ACLK                    22
+#define CLK_GOUT_DPU_SSMT_DPU0_PCLK                    23
+#define CLK_GOUT_DPU_SSMT_DPU1_ACLK                    24
+#define CLK_GOUT_DPU_SSMT_DPU1_PCLK                    25
+#define CLK_GOUT_DPU_SSMT_DPU2_ACLK                    26
+#define CLK_GOUT_DPU_SSMT_DPU2_PCLK                    27
+#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1               28
+#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2               29
+#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1               30
+#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2               31
+#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1               32
+#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2               33
+#define CLK_GOUT_DPU_SYSREG_DPU_PCLK                   34
+
 /* CMU_HSI0 */
 #define CLK_FOUT_USB_PLL                                       1
 #define CLK_MOUT_PLL_USB                                       2