CONFIG_PWM_BCM2835=y
CONFIG_PWM_SYSFS=y
CONFIG_RASPBERRYPI_FIRMWARE=y
+CONFIG_RASPBERRYPI_POWER=y
CONFIG_RATIONAL=y
CONFIG_RAW_DRIVER=y
# CONFIG_RCU_STALL_COMMON is not set
CONFIG_PWM_BCM2835=y
CONFIG_PWM_SYSFS=y
CONFIG_RASPBERRYPI_FIRMWARE=y
+CONFIG_RASPBERRYPI_POWER=y
CONFIG_RATIONAL=y
CONFIG_RAW_DRIVER=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_PWM_BCM2835=y
CONFIG_PWM_SYSFS=y
CONFIG_RASPBERRYPI_FIRMWARE=y
+CONFIG_RASPBERRYPI_POWER=y
CONFIG_RATIONAL=y
CONFIG_RAW_DRIVER=y
CONFIG_RCU_STALL_COMMON=y
$(eval $(call KernelPackage,sound-soc-bcm2835-i2s))
+define KernelPackage/sound-soc-boomberry-dac
+ TITLE:=Support for BoomBerry DAC
+ KCONFIG:= \
+ CONFIG_SND_BCM2708_SOC_BOOMBERRY_DAC \
+ CONFIG_SND_SOC_PCM512x
+ FILES:= \
+ $(LINUX_DIR)/sound/soc/bcm/snd-soc-boomberry-dac.ko \
+ $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko
+ AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x snd-soc-boomberry-dac)
+ DEPENDS:= \
+ kmod-sound-soc-bcm2835-i2s \
+ +kmod-i2c-bcm2708
+ $(call AddDepends/sound)
+endef
+
+define KernelPackage/sound-soc-boomberry-dac/description
+ This package contains support for BoomBerry DAC
+endef
+
+$(eval $(call KernelPackage,sound-soc-boomberry-dac))
+
+define KernelPackage/sound-soc-boomberry-digi
+ TITLE:=Support for BoomBerry Digi
+ KCONFIG:= \
+ CONFIG_SND_BCM2708_SOC_BOOMBERRY_DIGI \
+ CONFIG_SND_SOC_WM8804
+ FILES:= \
+ $(LINUX_DIR)/sound/soc/bcm/snd-soc-boomberry-digi.ko \
+ $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko
+ AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8804 snd-soc-boomberry-digi)
+ DEPENDS:= \
+ kmod-sound-soc-bcm2835-i2s \
+ +kmod-i2c-bcm2708
+ $(call AddDepends/sound)
+endef
+
+define KernelPackage/sound-soc-boomberry-digi/description
+ This package contains support for BoomBerry Digi
+endef
+
+$(eval $(call KernelPackage,sound-soc-boomberry-digi))
+
define KernelPackage/sound-soc-hifiberry-dac
TITLE:=Support for HifiBerry DAC
KCONFIG:= \
-From 23b133903a357066adb48bceb76aba8bd30d8c66 Mon Sep 17 00:00:00 2001
+From e3aec450775ffe2df234b44a59b66800eeff00c8 Mon Sep 17 00:00:00 2001
From: Steve Glendinning <steve.glendinning@smsc.com>
Date: Thu, 19 Feb 2015 18:47:12 +0000
-Subject: [PATCH 001/232] smsx95xx: fix crimes against truesize
+Subject: [PATCH 001/304] smsx95xx: fix crimes against truesize
smsc95xx is adjusting truesize when it shouldn't, and following a recent patch from Eric this is now triggering warnings.
-From e7515ee9af1d150d50b55d8f8f53d735a23cb253 Mon Sep 17 00:00:00 2001
+From c8fa4edd9b4f1dbc6c8edc80643bd08070d9e4a9 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Fri, 17 Apr 2015 16:58:45 +0100
-Subject: [PATCH 002/232] smsc95xx: Disable turbo mode by default
+Subject: [PATCH 002/304] smsc95xx: Disable turbo mode by default
---
drivers/net/usb/smsc95xx.c | 2 +-
-From 849ff5353023c95d40040ecfd279e216074b3d1c Mon Sep 17 00:00:00 2001
+From 9a7ab264528085a6838fb176e6ea518e4cd2cc18 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 18 Jun 2014 13:42:01 +0100
-Subject: [PATCH 003/232] vmstat: Workaround for issue where dirty page count
+Subject: [PATCH 003/304] vmstat: Workaround for issue where dirty page count
goes negative
See:
-From d29365673ed37e7688bd3f35c4a5ad719f878190 Mon Sep 17 00:00:00 2001
+From 5562d1c3a783a1384a6502e9c7ef63756fffb4a8 Mon Sep 17 00:00:00 2001
From: Robert Tiemann <rtie@gmx.de>
Date: Mon, 20 Jul 2015 11:01:25 +0200
-Subject: [PATCH 004/232] BCM2835_DT: Fix I2S register map
+Subject: [PATCH 004/304] BCM2835_DT: Fix I2S register map
---
Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 4 ++--
-From c891de13b385afb3e4b2c97ac5bbea7e2d97252f Mon Sep 17 00:00:00 2001
+From a072785b4d4e3290bb1992fa97009562b8cbcee3 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 4 Dec 2015 17:41:50 +0000
-Subject: [PATCH 005/232] irq-bcm2836: Prevent spurious interrupts, and trap
+Subject: [PATCH 005/304] irq-bcm2836: Prevent spurious interrupts, and trap
them early
The old arch-specific IRQ macros included a dsb to ensure the
-From 60f7ee79b375d72f5ef46ec542b925b1f1428bad Mon Sep 17 00:00:00 2001
+From 0551c5ca00a862c2902bd3640aa08f948332e525 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Fri, 12 Jun 2015 19:01:05 +0200
-Subject: [PATCH 006/232] irqchip: bcm2835: Add FIQ support
+Subject: [PATCH 006/304] irqchip: bcm2835: Add FIQ support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 890dccbb9c60be182adefb61b3ede805ccba1a91 Mon Sep 17 00:00:00 2001
+From dd7d7256191e694771fffcc05c9c43e0ca77b724 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Fri, 23 Oct 2015 16:26:55 +0200
-Subject: [PATCH 007/232] irqchip: irq-bcm2835: Add 2836 FIQ support
+Subject: [PATCH 007/304] irqchip: irq-bcm2835: Add 2836 FIQ support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 9a27662aac88f95b3de1915333a0265614f88a0d Mon Sep 17 00:00:00 2001
+From a1c1d55bb480c9d67814d0a965efdaabb83b4f85 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 30 Jun 2015 14:12:42 +0100
-Subject: [PATCH 008/232] serial: 8250: Don't crash when nr_uarts is 0
+Subject: [PATCH 008/304] serial: 8250: Don't crash when nr_uarts is 0
---
drivers/tty/serial/8250/8250_core.c | 2 ++
-From 4d7ff05e4d4d8d8adb4e7b4dd5fa8f63ae2be0f6 Mon Sep 17 00:00:00 2001
+From faa0db48929e02320294b4bb6b40c3478aee984e Mon Sep 17 00:00:00 2001
From: notro <notro@tronnes.org>
Date: Thu, 10 Jul 2014 13:59:47 +0200
-Subject: [PATCH 009/232] pinctrl-bcm2835: Set base to 0 give expected gpio
+Subject: [PATCH 009/304] pinctrl-bcm2835: Set base to 0 give expected gpio
numbering
Signed-off-by: Noralf Tronnes <notro@tronnes.org>
-From 969dc44a700e1be13c3f80445d40c1fe51cc4370 Mon Sep 17 00:00:00 2001
+From ae53bc0b0589b078b38bcd662aaa1589506d3108 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 24 Feb 2015 13:40:50 +0000
-Subject: [PATCH 010/232] pinctrl-bcm2835: Fix interrupt handling for GPIOs
+Subject: [PATCH 010/304] pinctrl-bcm2835: Fix interrupt handling for GPIOs
28-31 and 46-53
Contrary to the documentation, the BCM2835 GPIO controller actually has
-From b949246bf51fa852bad45136cdd6bcd91a29539e Mon Sep 17 00:00:00 2001
+From 6b21816af06720e064a2f84ddafb858692c25472 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Thu, 26 Feb 2015 09:58:22 +0000
-Subject: [PATCH 011/232] pinctrl-bcm2835: Only request the interrupts listed
+Subject: [PATCH 011/304] pinctrl-bcm2835: Only request the interrupts listed
in the DTB
Although the GPIO controller can generate three interrupts (four counting
-From 19bcdacc5a67abe6a2d604a39ddfed5a54c77b2e Mon Sep 17 00:00:00 2001
+From f685e187de2908b8b6399055a972e841a6e8e97a Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 24 Jun 2015 14:10:44 +0100
-Subject: [PATCH 012/232] spi-bcm2835: Support pin groups other than 7-11
+Subject: [PATCH 012/304] spi-bcm2835: Support pin groups other than 7-11
The spi-bcm2835 driver automatically uses GPIO chip-selects due to
some unreliability of the native ones. In doing so it chooses the
-From 7ce5cbfba6e930c2178f342a4390972f1efd75ef Mon Sep 17 00:00:00 2001
+From 7f7e20a0070ff81ced9eb8eedd8efc19af959605 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Wed, 3 Jun 2015 12:26:13 +0200
-Subject: [PATCH 013/232] ARM: bcm2835: Set Serial number and Revision
+Subject: [PATCH 013/304] ARM: bcm2835: Set Serial number and Revision
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 569baa856d805e594011f2d1444b6849c291544d Mon Sep 17 00:00:00 2001
+From 61037c6b43a4e3f1a53582fb92ee7f964b6bace5 Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Sun, 11 Oct 2015 16:44:05 +0200
-Subject: [PATCH 014/232] bcm2835-i2s: get base address for DMA from devicetree
+Subject: [PATCH 014/304] bcm2835-i2s: get base address for DMA from devicetree
Code copied from spi-bcm2835. Get physical address from devicetree
instead of using hardcoded constant.
-From c61a7aef15a1aee86e1de59dca2ad7002995f9cf Mon Sep 17 00:00:00 2001
+From 09feefa33b3f36291dc3a406bcf80dddf72568e9 Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Sun, 11 Oct 2015 15:21:16 +0200
-Subject: [PATCH 015/232] bcm2835-i2s: add 24bit support, update bclk_ratio to
+Subject: [PATCH 015/304] bcm2835-i2s: add 24bit support, update bclk_ratio to
more correct values
Code ported from bcm2708-i2s driver in Raspberry Pi tree.
-From e2a75ce0e2b6319150e14401f9822adba7895c9c Mon Sep 17 00:00:00 2001
+From b10789f9366de21dc44df087c4e65aa4a56a1dd9 Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Sun, 11 Oct 2015 15:25:51 +0200
-Subject: [PATCH 016/232] bcm2835-i2s: setup clock only if CPU is clock master
+Subject: [PATCH 016/304] bcm2835-i2s: setup clock only if CPU is clock master
Code ported from bcm2708-i2s driver in Raspberry Pi tree.
-From 433841fc5958e1ddbd503b579a022fb67defd74b Mon Sep 17 00:00:00 2001
+From 08c03b0127c99d816f84a03d9f62c2b8313b359e Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Sun, 11 Oct 2015 15:49:51 +0200
-Subject: [PATCH 017/232] bcm2835-i2s: Eliminate debugfs directory error
+Subject: [PATCH 017/304] bcm2835-i2s: Eliminate debugfs directory error
Code ported from bcm2708-i2s driver in Raspberry Pi tree.
-From 7b4481818fe920904457496db40d59dd3d0a83bb Mon Sep 17 00:00:00 2001
+From 6eb24a344f83c6b0768e6e63fa1865d3f444ed5a Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Sun, 11 Oct 2015 15:35:20 +0200
-Subject: [PATCH 018/232] bcm2835-i2s: Register PCM device
+Subject: [PATCH 018/304] bcm2835-i2s: Register PCM device
Code ported from bcm2708-i2s driver in Raspberry Pi tree.
-From 027ba808e84799c97ae1c64f8424ac8eb7235cc4 Mon Sep 17 00:00:00 2001
+From 0c4d87b48e1ec19d0de0ceae22981647a927a83a Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Sun, 11 Oct 2015 15:55:21 +0200
-Subject: [PATCH 019/232] bcm2835-i2s: Enable MMAP support via a DT property
+Subject: [PATCH 019/304] bcm2835-i2s: Enable MMAP support via a DT property
Code ported from bcm2708-i2s driver in Raspberry Pi tree.
-From 8a349301238aabb40c9da5ca8c8492b6b8d146f6 Mon Sep 17 00:00:00 2001
+From b2a69d30bbcbf96f6469a7cab9f9831351ea3d75 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Thu, 9 Apr 2015 12:34:11 +0200
-Subject: [PATCH 020/232] dmaengine: bcm2835: Add slave dma support
+Subject: [PATCH 020/304] dmaengine: bcm2835: Add slave dma support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 290f55520c62025da992d6be0002fc1e3738cfdb Mon Sep 17 00:00:00 2001
+From 6018cc9ef34ff7c465cf5c7674de004facf9bec8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Sat, 3 Oct 2015 15:58:59 +0200
-Subject: [PATCH 021/232] dmaengine: bcm2835: set residue_granularity field
+Subject: [PATCH 021/304] dmaengine: bcm2835: set residue_granularity field
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 6f56fff39c811953809b011f59c49a2122c4d173 Mon Sep 17 00:00:00 2001
+From 64eb22fa4c7f019d40afc335d780079dfc52de91 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Sat, 3 Oct 2015 22:22:55 +0200
-Subject: [PATCH 022/232] dmaengine: bcm2835: Load driver early and support
+Subject: [PATCH 022/304] dmaengine: bcm2835: Load driver early and support
legacy API
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
-From df03f00c5e21559185b5a61ea5e8238e10959ab1 Mon Sep 17 00:00:00 2001
+From b28f69e34f275f12d22b469f8ed74de076c058fb Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Sat, 10 Oct 2015 12:29:18 +0200
-Subject: [PATCH 023/232] bcm2835-dma: Fix dreq not set for slave transfers
+Subject: [PATCH 023/304] bcm2835-dma: Fix dreq not set for slave transfers
Set dreq to slave_id if it is not set like in bcm2708-dmaengine.
---
-From 052c2005b6ecedc5abad86632f5781adda310aa7 Mon Sep 17 00:00:00 2001
+From 2de86278755ccd71765ff6c658295a825ae85bcd Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Sun, 11 Oct 2015 12:28:30 +0200
-Subject: [PATCH 024/232] bcm2835-dma: Limit cyclic transfers on lite channels
+Subject: [PATCH 024/304] bcm2835-dma: Limit cyclic transfers on lite channels
to 32k
Transfers larger than 32k cause repeated clicking with I2S soundcards.
-From a72021ae99021409319d552dad744572b20febfb Mon Sep 17 00:00:00 2001
+From 03eed3ba7f50f36bfe465aff568bbdf6c7e9505a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Sat, 15 Aug 2015 20:50:02 +0200
-Subject: [PATCH 025/232] bcm2835: Add support for uart1
+Subject: [PATCH 025/304] bcm2835: Add support for uart1
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 4364707caa6d3d9edf84fa8469a04f33e1ba5d76 Mon Sep 17 00:00:00 2001
+From 494564a4ddb2a550ec340dee8ffd46de8faa8267 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Fri, 26 Jun 2015 14:21:20 +0200
-Subject: [PATCH 026/232] firmware: bcm2835: Add missing property tags
+Subject: [PATCH 026/304] firmware: bcm2835: Add missing property tags
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From cd721670ab8c729d0c62e99a1d173c2575b63282 Mon Sep 17 00:00:00 2001
+From 65fc8b10fa17a19d8c92a1b7a601e47a749060b6 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Sun, 12 May 2013 12:24:19 +0100
-Subject: [PATCH 027/232] Main bcm2708/bcm2709 linux port
+Subject: [PATCH 027/304] Main bcm2708/bcm2709 linux port
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 812484cc27980e3351360200478e7044de983f40 Mon Sep 17 00:00:00 2001
+From fc29614ab47f681dafa8e72e785df2608c542619 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 11 Nov 2015 21:01:15 +0000
-Subject: [PATCH 028/232] squash: include ARCH_BCM2708 / ARCH_BCM2709
+Subject: [PATCH 028/304] squash: include ARCH_BCM2708 / ARCH_BCM2709
---
drivers/char/hw_random/Kconfig | 2 +-
-From 7efc2851a46faa1aceda5f6ec255d0e814812ccf Mon Sep 17 00:00:00 2001
+From e3bac792b4c542025127f57394356e5c495e75dc Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 1 May 2013 19:46:17 +0100
-Subject: [PATCH 029/232] Add dwc_otg driver
+Subject: [PATCH 029/304] Add dwc_otg driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From d3b7394edae550f295e185be4651ed43529e7042 Mon Sep 17 00:00:00 2001
+From c8719ed281ffb6b738af0e8acc16aa13c0381749 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 17 Jun 2015 17:06:34 +0100
-Subject: [PATCH 030/232] bcm2708 framebuffer driver
+Subject: [PATCH 030/304] bcm2708 framebuffer driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 99b7c3cfd05f5898e96d7c44c5970880f2c0cd16 Mon Sep 17 00:00:00 2001
+From 451d996dcc4cc8460fea6b74331aaa762823d312 Mon Sep 17 00:00:00 2001
From: Florian Meier <florian.meier@koalo.de>
Date: Fri, 22 Nov 2013 14:22:53 +0100
-Subject: [PATCH 031/232] dmaengine: Add support for BCM2708
+Subject: [PATCH 031/304] dmaengine: Add support for BCM2708
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 65c8aadfd88010efb2d2a2821fea7aac978b6c78 Mon Sep 17 00:00:00 2001
+From 231ef69db2b015b7da9994ef893090206bf5f63f Mon Sep 17 00:00:00 2001
From: gellert <gellert@raspberrypi.org>
Date: Fri, 15 Aug 2014 16:35:06 +0100
-Subject: [PATCH 032/232] MMC: added alternative MMC driver
+Subject: [PATCH 032/304] MMC: added alternative MMC driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From c58bec0d84082837415562c6567396e9e5ba62f7 Mon Sep 17 00:00:00 2001
+From 73744a39303ad063a4b964a2bc48391be72c9310 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 25 Mar 2015 17:49:47 +0000
-Subject: [PATCH 033/232] Adding bcm2835-sdhost driver, and an overlay to
+Subject: [PATCH 033/304] Adding bcm2835-sdhost driver, and an overlay to
enable it
BCM2835 has two SD card interfaces. This driver uses the other one.
-From 36d8db53953365eecdf56695944e9f9919634de0 Mon Sep 17 00:00:00 2001
+From 7d966829e3d7a49f3efc033f41902c52edc2e07d Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 3 Jul 2013 00:31:47 +0100
-Subject: [PATCH 034/232] cma: Add vc_cma driver to enable use of CMA
+Subject: [PATCH 034/304] cma: Add vc_cma driver to enable use of CMA
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 2dd634f97c4fb77d9e81be289a8da29c390a0309 Mon Sep 17 00:00:00 2001
+From 03aa66334a94cbdaac80f3673a2e6e766b29ff32 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Mon, 26 Mar 2012 22:15:50 +0100
-Subject: [PATCH 035/232] bcm2708: alsa sound driver
+Subject: [PATCH 035/304] bcm2708: alsa sound driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 112360f76c91c892f1a29825eb2807bbf86ac67d Mon Sep 17 00:00:00 2001
+From b1e77a013c963839cd74707aa58532286cfacfcc Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Tue, 2 Jul 2013 23:42:01 +0100
-Subject: [PATCH 036/232] bcm2708 vchiq driver
+Subject: [PATCH 036/304] bcm2708 vchiq driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From b0acaf43055bacef7918c835517ff6ea7da26e83 Mon Sep 17 00:00:00 2001
+From afecc66589fdfd0dcfde79917a82c51172d6c002 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 17 Jun 2015 16:07:06 +0100
-Subject: [PATCH 037/232] vc_mem: Add vc_mem driver
+Subject: [PATCH 037/304] vc_mem: Add vc_mem driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 5f05accd033e4b032f64717a0276d7174f697919 Mon Sep 17 00:00:00 2001
+From cd630a79b98d0406559589a658c0d0b206e523bc Mon Sep 17 00:00:00 2001
From: Tim Gover <tgover@broadcom.com>
Date: Tue, 22 Jul 2014 15:41:04 +0100
-Subject: [PATCH 038/232] vcsm: VideoCore shared memory service for BCM2835
+Subject: [PATCH 038/304] vcsm: VideoCore shared memory service for BCM2835
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 1ee3b49a62efe1416a6b40fb5c6032288f3d2b08 Mon Sep 17 00:00:00 2001
+From e2633bbfb7a44ca624c5c67df3cab9e39e8357cf Mon Sep 17 00:00:00 2001
From: Luke Wren <luke@raspberrypi.org>
Date: Fri, 21 Aug 2015 23:14:48 +0100
-Subject: [PATCH 039/232] Add /dev/gpiomem device for rootless user GPIO access
+Subject: [PATCH 039/304] Add /dev/gpiomem device for rootless user GPIO access
Signed-off-by: Luke Wren <luke@raspberrypi.org>
-From e19c303e7d54d986e0bd3e47107a83e30329c1d0 Mon Sep 17 00:00:00 2001
+From 2c8e4852592e64f426a482df8b662984bb4f6c9e Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Sat, 5 Sep 2015 01:14:45 +0100
-Subject: [PATCH 040/232] Add SMI driver
+Subject: [PATCH 040/304] Add SMI driver
Signed-off-by: Luke Wren <wren6991@gmail.com>
---
-From c0fe401b61ae4d002f6fc84438ce69c5917c580a Mon Sep 17 00:00:00 2001
+From 810a555a6fe83edc69126deba240839f152d8938 Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Sat, 5 Sep 2015 01:16:10 +0100
-Subject: [PATCH 041/232] Add SMI NAND driver
+Subject: [PATCH 041/304] Add SMI NAND driver
Signed-off-by: Luke Wren <wren6991@gmail.com>
---
-From 0bc00c67aea43098c7b066e7b123379b260cc7de Mon Sep 17 00:00:00 2001
+From 1f298174c176aa408de36b46421ac114357ac0e9 Mon Sep 17 00:00:00 2001
From: Aron Szabo <aron@aron.ws>
Date: Sat, 16 Jun 2012 12:15:55 +0200
-Subject: [PATCH 042/232] lirc: added support for RaspberryPi GPIO
+Subject: [PATCH 042/304] lirc: added support for RaspberryPi GPIO
lirc_rpi: Use read_current_timer to determine transmitter delay. Thanks to jjmz and others
See: https://github.com/raspberrypi/linux/issues/525
-From 007ef35b2cf5d8a0197e81e712b38fb72cebae2e Mon Sep 17 00:00:00 2001
+From 3d01c18ff8973905ef050b20b13063f9e7759c3a Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 3 Jul 2013 00:49:20 +0100
-Subject: [PATCH 043/232] Add cpufreq driver
+Subject: [PATCH 043/304] Add cpufreq driver
Signed-off-by: popcornmix <popcornmix@gmail.com>
---
-From 9f251fdbaaf3bd895c2901413748679d68a0c644 Mon Sep 17 00:00:00 2001
+From a1dd93ad1499de093098226931462628cc86e4e6 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Tue, 26 Mar 2013 19:24:24 +0000
-Subject: [PATCH 044/232] Added hwmon/thermal driver for reporting core
+Subject: [PATCH 044/304] Added hwmon/thermal driver for reporting core
temperature. Thanks Dorian
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
-From 28a4399bf03eeb3ec5b7b56c9445b296e1427665 Mon Sep 17 00:00:00 2001
+From 0feef39a2329ed935108d53e02fe38cb4578dfbf Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 17 Jun 2015 15:44:08 +0100
-Subject: [PATCH 045/232] Add Chris Boot's i2c driver
+Subject: [PATCH 045/304] Add Chris Boot's i2c driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 75804edaed6c45d813dcee866d39445130d82539 Mon Sep 17 00:00:00 2001
+From 3423e9a9b7e0d6e988832d1362f2fb3ce76bf07c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Fri, 26 Jun 2015 14:27:06 +0200
-Subject: [PATCH 046/232] char: broadcom: Add vcio module
+Subject: [PATCH 046/304] char: broadcom: Add vcio module
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From 80b7c5e2cc3d633b3d3a1afbdb537e2ccfe906c7 Mon Sep 17 00:00:00 2001
+From f259f2e35226640b67ff324789f3638a724bab53 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Fri, 26 Jun 2015 14:25:01 +0200
-Subject: [PATCH 047/232] firmware: bcm2835: Support ARCH_BCM270x
+Subject: [PATCH 047/304] firmware: bcm2835: Support ARCH_BCM270x
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From e15fddd4332bd3a762d0feef48ff2b5e3df10af0 Mon Sep 17 00:00:00 2001
+From 877bf225ae61519f04b880abe2d84ae7dc585475 Mon Sep 17 00:00:00 2001
From: Vincent Sanders <vincent.sanders@collabora.co.uk>
Date: Wed, 30 Jan 2013 12:45:18 +0000
-Subject: [PATCH 048/232] bcm2835: add v4l2 camera device
+Subject: [PATCH 048/304] bcm2835: add v4l2 camera device
- Supports raw YUV capture, preview, JPEG and H264.
- Uses videobuf2 for data transfer, using dma_buf.
-From 91e833ab0b220bb0bb810bb9605b0a03cd76baa8 Mon Sep 17 00:00:00 2001
+From 35361c41437a4d81c47bc56189369201c5f1d2e4 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 11 May 2015 09:00:42 +0100
-Subject: [PATCH 049/232] scripts: Add mkknlimg and knlinfo scripts from tools
+Subject: [PATCH 049/304] scripts: Add mkknlimg and knlinfo scripts from tools
repo
The Raspberry Pi firmware looks for a trailer on the kernel image to
-From 918b9e451bbaebb775725a292fd3b6e3d4cf804f Mon Sep 17 00:00:00 2001
+From e88c206c101194b8513860c135ee77366d7456eb Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 5 Dec 2014 17:26:26 +0000
-Subject: [PATCH 050/232] fdt: Add support for the CONFIG_CMDLINE_EXTEND option
+Subject: [PATCH 050/304] fdt: Add support for the CONFIG_CMDLINE_EXTEND option
---
drivers/of/fdt.c | 29 ++++++++++++++++++++++++-----
-From d1fdaf68df66e82bea1081b490ebeea414d69203 Mon Sep 17 00:00:00 2001
+From f3552e720773b9e13a0667606c8438ae14d0538b Mon Sep 17 00:00:00 2001
From: notro <notro@tronnes.org>
Date: Wed, 9 Jul 2014 14:46:08 +0200
-Subject: [PATCH 051/232] BCM2708: Add core Device Tree support
+Subject: [PATCH 051/304] BCM2708: Add core Device Tree support
Add the bare minimum needed to boot BCM2708 from a Device Tree.
-From da7cdef4979282624e0e7527c3c8334a59f39676 Mon Sep 17 00:00:00 2001
+From 96c7eeec2f269f779e14eef94e19804f70ac5c36 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Sat, 15 Aug 2015 20:47:07 +0200
-Subject: [PATCH 052/232] bcm2835: Match with BCM2708 Device Trees
+Subject: [PATCH 052/304] bcm2835: Match with BCM2708 Device Trees
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From b28366cb5b514e5c59586f9a5509d3afff5337d5 Mon Sep 17 00:00:00 2001
+From 2d65eb731311b3bb43ac2b2194d76be99246aefc Mon Sep 17 00:00:00 2001
From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Date: Mon, 17 Jun 2013 13:32:11 +0300
-Subject: [PATCH 053/232] fbdev: add FBIOCOPYAREA ioctl
+Subject: [PATCH 053/304] fbdev: add FBIOCOPYAREA ioctl
Based on the patch authored by Ali Gholami Rudi at
https://lkml.org/lkml/2009/7/13/153
-From dbf03b37592b79d891cb796fda13d8495a6a5234 Mon Sep 17 00:00:00 2001
+From 2b0758010872540fd290ed5c3ab489f7318fc977 Mon Sep 17 00:00:00 2001
From: Harm Hanemaaijer <fgenfb@yahoo.com>
Date: Thu, 20 Jun 2013 20:21:39 +0200
-Subject: [PATCH 057/232] Speed up console framebuffer imageblit function
+Subject: [PATCH 057/304] Speed up console framebuffer imageblit function
Especially on platforms with a slower CPU but a relatively high
framebuffer fill bandwidth, like current ARM devices, the existing
-From cf63ba6ba21e8a1d62b1eb4917af42d6bcfa4445 Mon Sep 17 00:00:00 2001
+From eec29af59aca3d4f7edd6760c12ff33e8650d20d Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Tue, 26 Mar 2013 17:26:38 +0000
-Subject: [PATCH 058/232] Allow mac address to be set in smsc95xx
+Subject: [PATCH 058/304] Allow mac address to be set in smsc95xx
Signed-off-by: popcornmix <popcornmix@gmail.com>
---
-From 20f0537c77ac3ef4e446bd0013c37ddd3af3936b Mon Sep 17 00:00:00 2001
+From cb3ff14d3ee1bfb19828f1f48fe486f33d7a6fbb Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 8 May 2013 11:46:50 +0100
-Subject: [PATCH 059/232] enabling the realtime clock 1-wire chip DS1307 and
+Subject: [PATCH 059/304] enabling the realtime clock 1-wire chip DS1307 and
1-wire on GPIO4 (as a module)
1-wire: Add support for configuring pin for w1-gpio kernel module
-From fbd8454a22771ed12e1905a52934a6a871bc492e Mon Sep 17 00:00:00 2001
+From b0237d9659cb376e049e205dd9db20c210237388 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 3 Jul 2013 00:54:08 +0100
-Subject: [PATCH 060/232] Added Device IDs for August DVB-T 205
+Subject: [PATCH 060/304] Added Device IDs for August DVB-T 205
---
drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 4 ++++
-From 6f8e2aeb77e4437eab3a46d74a1a2b9533812c81 Mon Sep 17 00:00:00 2001
+From 2cf0ecd618278861b4f7a9e7b72f39974493e18d Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 18 Dec 2013 22:16:19 +0000
-Subject: [PATCH 061/232] config: Enable CONFIG_MEMCG, but leave it disabled
+Subject: [PATCH 061/304] config: Enable CONFIG_MEMCG, but leave it disabled
(due to memory cost). Enable with cgroup_enable=memory.
---
-From b507ac15b579d88a09bf915f2f3ca8de7f1e4bf7 Mon Sep 17 00:00:00 2001
+From 6566720748ca71f63386608bb4c72e3b1efcc43a Mon Sep 17 00:00:00 2001
From: Florian Meier <florian.meier@koalo.de>
Date: Fri, 22 Nov 2013 14:59:51 +0100
-Subject: [PATCH 062/232] ASoC: Add support for PCM5102A codec
+Subject: [PATCH 062/304] ASoC: Add support for PCM5102A codec
Some definitions to support the PCM5102A codec
by Texas Instruments.
-From 9f5e88b201753c68a90fa45a269aa82febc58fc6 Mon Sep 17 00:00:00 2001
+From d47c284760f870b312b4ed488b71d0b549e0ef70 Mon Sep 17 00:00:00 2001
From: Florian Meier <florian.meier@koalo.de>
Date: Fri, 22 Nov 2013 19:19:08 +0100
-Subject: [PATCH 063/232] ASoC: Add support for HifiBerry DAC
+Subject: [PATCH 063/304] ASoC: Add support for HifiBerry DAC
This adds a machine driver for the HifiBerry DAC.
It is a sound card that can
-From 95bf71f0e826b97bad98f350e2fee6ba515a38cf Mon Sep 17 00:00:00 2001
+From 26ee57a5d9cd05e006b277446c9535aeda3c93d6 Mon Sep 17 00:00:00 2001
From: Florian Meier <florian.meier@koalo.de>
Date: Fri, 22 Nov 2013 19:21:34 +0100
-Subject: [PATCH 064/232] ASoC: Add support for Rpi-DAC
+Subject: [PATCH 064/304] ASoC: Add support for Rpi-DAC
---
sound/soc/bcm/Kconfig | 7 +++
-From 455d188d2a22ced675219587856c0dc66efc7256 Mon Sep 17 00:00:00 2001
+From ca1252c2232d7a7d44c8ae1fc35ae11ef2cd860d Mon Sep 17 00:00:00 2001
From: Daniel Matuschek <info@crazy-audio.com>
Date: Wed, 15 Jan 2014 21:41:23 +0100
-Subject: [PATCH 065/232] ASoC: wm8804: Implement MCLK configuration options,
+Subject: [PATCH 065/304] ASoC: wm8804: Implement MCLK configuration options,
add 32bit support WM8804 can run with PLL frequencies of 256xfs and 128xfs
for most sample rates. At 192kHz only 128xfs is supported. The existing
driver selects 128xfs automatically for some lower samples rates. By using an
-From 442de6ae737fbd27bcf2fde8be857beccc59fd1f Mon Sep 17 00:00:00 2001
+From 376d0b5d94c6d78d943f30b81de14bc66f7b2911 Mon Sep 17 00:00:00 2001
From: Daniel Matuschek <info@crazy-audio.com>
Date: Wed, 15 Jan 2014 21:42:08 +0100
-Subject: [PATCH 066/232] ASoC: BCM:Add support for HiFiBerry Digi. Driver is
+Subject: [PATCH 066/304] ASoC: BCM:Add support for HiFiBerry Digi. Driver is
based on the patched WM8804 driver.
Signed-off-by: Daniel Matuschek <daniel@matuschek.net>
-From 836e7d5d46f17115b728986e3077c78c211a7678 Mon Sep 17 00:00:00 2001
+From b271e01a647c30ff8c6e66b2d4109e72235da27d Mon Sep 17 00:00:00 2001
From: Daniel Matuschek <info@crazy-audio.com>
Date: Thu, 16 Jan 2014 07:36:35 +0100
-Subject: [PATCH 067/232] ASoC: wm8804: Set idle_bias_off to false Idle bias
+Subject: [PATCH 067/304] ASoC: wm8804: Set idle_bias_off to false Idle bias
has been change to remove warning on driver startup
Signed-off-by: Daniel Matuschek <daniel@matuschek.net>
-From 7ab81054051a41288e4aa2bb21d4740e0d78a4ac Mon Sep 17 00:00:00 2001
+From 21af89410a1ca12bce1dcfcd49af1eea66437af9 Mon Sep 17 00:00:00 2001
From: Gordon Garrity <gordon@iqaudio.com>
Date: Sat, 8 Mar 2014 16:56:57 +0000
-Subject: [PATCH 068/232] Add IQaudIO Sound Card support for Raspberry Pi
+Subject: [PATCH 068/304] Add IQaudIO Sound Card support for Raspberry Pi
Set a limit of 0dB on Digital Volume Control
-From efb984b47e685c966a3b55874de2c1fb5b0b1140 Mon Sep 17 00:00:00 2001
+From 1aaeb4fd759f159edc94ed53c7e1d02a57a107ae Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Mon, 14 Jul 2014 22:02:09 +0100
-Subject: [PATCH 069/232] hid: Reduce default mouse polling interval to 60Hz
+Subject: [PATCH 069/304] hid: Reduce default mouse polling interval to 60Hz
Reduces overhead when using X
---
-From 72a92f2e40881dcb46e50021c5c5fe2c20d8c461 Mon Sep 17 00:00:00 2001
+From bdc06975313393c21c0f72d52f1733a2333d1b70 Mon Sep 17 00:00:00 2001
From: Daniel Matuschek <info@crazy-audio.com>
Date: Mon, 4 Aug 2014 10:06:56 +0200
-Subject: [PATCH 070/232] Added support for HiFiBerry DAC+
+Subject: [PATCH 070/304] Added support for HiFiBerry DAC+
The driver is based on the HiFiBerry DAC driver. However HiFiBerry DAC+ uses
a different codec chip (PCM5122), therefore a new driver is necessary.
-From f25572414689152e6208e5ca921185b1db536b24 Mon Sep 17 00:00:00 2001
+From 1d152bc8e97a3f004604ff4c10e5243266b4a312 Mon Sep 17 00:00:00 2001
From: Daniel Matuschek <info@crazy-audio.com>
Date: Mon, 4 Aug 2014 11:09:58 +0200
-Subject: [PATCH 071/232] Added driver for HiFiBerry Amp amplifier add-on board
+Subject: [PATCH 071/304] Added driver for HiFiBerry Amp amplifier add-on board
The driver contains a low-level hardware driver for the TAS5713 and the
drivers for the Raspberry Pi I2S subsystem.
-From d0bfff366e12c9b401ac7eafabab7337e82549ea Mon Sep 17 00:00:00 2001
+From 455ba80fce771499a5045cfddd741895f38cbc01 Mon Sep 17 00:00:00 2001
From: Ryan Coe <bluemrp9@gmail.com>
Date: Sat, 31 Jan 2015 18:25:49 -0700
-Subject: [PATCH 072/232] Update ds1307 driver for device-tree support
+Subject: [PATCH 072/304] Update ds1307 driver for device-tree support
Signed-off-by: Ryan Coe <bluemrp9@gmail.com>
---
-From 96aac93fdea2caa77d4746aa001c2d792b314112 Mon Sep 17 00:00:00 2001
+From 0613a9ad697b96c7aa5f3b6cb7d0c3bb236428e8 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 6 Feb 2015 13:50:57 +0000
-Subject: [PATCH 073/232] BCM270x_DT: Add pwr_led, and the required "input"
+Subject: [PATCH 073/304] BCM270x_DT: Add pwr_led, and the required "input"
trigger
The "input" trigger makes the associated GPIO an input. This is to support
-From d3a1dcc1ce28233707c395b11cd2403ba22aebda Mon Sep 17 00:00:00 2001
+From 46c40754e960e05c4b7f0d76241e75b5363527d5 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 27 Feb 2015 15:10:24 +0000
-Subject: [PATCH 074/232] enc28j60: Add device tree compatible string and an
+Subject: [PATCH 074/304] enc28j60: Add device tree compatible string and an
overlay
---
-From a058f705de89cb54126d9bf8d099acb7ececb6e7 Mon Sep 17 00:00:00 2001
+From fd2629ca6b3487d6efe7c49c93cb44a47cbf9e5a Mon Sep 17 00:00:00 2001
From: Waldemar Brodkorb <wbrodkorb@conet.de>
Date: Wed, 25 Mar 2015 09:26:17 +0100
-Subject: [PATCH 075/232] Add driver for rpi-proto
+Subject: [PATCH 075/304] Add driver for rpi-proto
Forward port of 3.10.x driver from https://github.com/koalo
We are using a custom board and would like to use rpi 3.18.x
-From 78cf26e64b4ce0c4567829c42990a89ab59a6553 Mon Sep 17 00:00:00 2001
+From e892ae7922d86bdede4f59336222cb9d8cf60994 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Mon, 13 Apr 2015 17:16:29 +0100
-Subject: [PATCH 076/232] config: Add default configs
+Subject: [PATCH 076/304] config: Add default configs
---
arch/arm/configs/bcm2709_defconfig | 1254 +++++++++++++++++++++++++++++++++++
-From 0ee42e134a9a28fd825e1390634113108c0eebc0 Mon Sep 17 00:00:00 2001
+From b08ccdff6e3f9a0b17edaf423f140775a5a25c72 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Wed, 29 Apr 2015 17:24:02 +0200
-Subject: [PATCH 077/232] bcm2835: bcm2835_defconfig
+Subject: [PATCH 077/304] bcm2835: bcm2835_defconfig
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
-From d46fbf49354f8c82cc216d56d9addad113703c50 Mon Sep 17 00:00:00 2001
+From d9eaf4c9a302c60d131ce6e7384ae36085cf5731 Mon Sep 17 00:00:00 2001
From: Gordon Hollingworth <gordon@raspberrypi.org>
Date: Tue, 12 May 2015 14:47:56 +0100
-Subject: [PATCH 078/232] rpi-ft5406: Add touchscreen driver for pi LCD display
+Subject: [PATCH 078/304] rpi-ft5406: Add touchscreen driver for pi LCD display
Fix driver detection failure Check that the buffer response is non-zero meaning the touchscreen was detected
-From 4514b02d95de8be6d6298ee20a5204815cf669d0 Mon Sep 17 00:00:00 2001
+From 93aae11e6e1bcd5178685f85938e7c339d91a95e Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 13 Oct 2014 11:47:53 +0100
-Subject: [PATCH 079/232] Improve __copy_to_user and __copy_from_user
+Subject: [PATCH 079/304] Improve __copy_to_user and __copy_from_user
performance
Provide a __copy_from_user that uses memcpy. On BCM2708, use
-From 11e9f3f8268e79dd28450eacffe1d7484f2a7361 Mon Sep 17 00:00:00 2001
+From 328a04523323650c59fef1657143e87513c79751 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Thu, 25 Jun 2015 12:16:11 +0100
-Subject: [PATCH 080/232] gpio-poweroff: Allow it to work on Raspberry Pi
+Subject: [PATCH 080/304] gpio-poweroff: Allow it to work on Raspberry Pi
The Raspberry Pi firmware manages the power-down and reboot
process. To do this it installs a pm_power_off handler, causing
-From 958d09ad7f70ff5dd38a6c60b9e3f103e125168a Mon Sep 17 00:00:00 2001
+From c2c3af65be6009ded5c3c8984ab7f58f5e7797ee Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 14 Jul 2015 10:26:09 +0100
-Subject: [PATCH 081/232] spidev: Add "spidev" compatible string to silence
+Subject: [PATCH 081/304] spidev: Add "spidev" compatible string to silence
warning
See: https://github.com/raspberrypi/linux/issues/1054
-From 462447ecf49eb6dd6d77f3d21b272dd4fa68bee9 Mon Sep 17 00:00:00 2001
+From 7508b75a2466c9d6f9061fde718eb6bbfed44ede Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 14 Jul 2015 17:00:18 +0100
-Subject: [PATCH 082/232] scripts/dtc: Add overlay support
+Subject: [PATCH 082/304] scripts/dtc: Add overlay support
---
scripts/dtc/checks.c | 119 ++-
-From 98ec469c223432d4f40317023a04cfa71f661c10 Mon Sep 17 00:00:00 2001
+From 4969b05b74287320b646ec19371c1e04f1d98336 Mon Sep 17 00:00:00 2001
From: Phil Elwell <pelwell@users.noreply.github.com>
Date: Tue, 14 Jul 2015 14:32:47 +0100
-Subject: [PATCH 083/232] mfd: Add Raspberry Pi Sense HAT core driver
+Subject: [PATCH 083/304] mfd: Add Raspberry Pi Sense HAT core driver
---
drivers/input/joystick/Kconfig | 8 +
-From 5133d16d705f9ccf7f558ebc43861e1800512969 Mon Sep 17 00:00:00 2001
+From f8cf34f551e172b02306ce12da00e8c8c2550660 Mon Sep 17 00:00:00 2001
From: Jan Grulich <jan@grulich.eu>
Date: Mon, 24 Aug 2015 16:03:47 +0100
-Subject: [PATCH 084/232] RaspiDAC3 support
+Subject: [PATCH 084/304] RaspiDAC3 support
Signed-off-by: Jan Grulich <jan@grulich.eu>
-From 570d2d99cbf2b830e0d1be01dcc6fdd339b4d157 Mon Sep 17 00:00:00 2001
+From bdf67add80855689e7580feaa8ae1c82d2f9d209 Mon Sep 17 00:00:00 2001
From: Jan Grulich <jan@grulich.eu>
Date: Mon, 24 Aug 2015 16:02:34 +0100
-Subject: [PATCH 085/232] tpa6130a2: Add headphone switch control
+Subject: [PATCH 085/304] tpa6130a2: Add headphone switch control
Signed-off-by: Jan Grulich <jan@grulich.eu>
---
-From a9e2bfff9a39efe94a066735509643fc3bed1ba0 Mon Sep 17 00:00:00 2001
+From 19b6a85b13ed26364b6bb0946cf51ede345d8e2d Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Mon, 28 Sep 2015 23:38:59 +0100
-Subject: [PATCH 086/232] irq-bcm2835: Fix building with 2708
+Subject: [PATCH 086/304] irq-bcm2835: Fix building with 2708
---
drivers/irqchip/irq-bcm2835.c | 3 ++-
-From 0a8cace2c9d473ac347cc08dfe19b24ad5ca3d2b Mon Sep 17 00:00:00 2001
+From 6e7a4e8116e8379bd3be1d88092bfb9cacee7e14 Mon Sep 17 00:00:00 2001
From: P33M <P33M@github.com>
Date: Wed, 21 Oct 2015 14:55:21 +0100
-Subject: [PATCH 087/232] rpi_display: add backlight driver and overlay
+Subject: [PATCH 087/304] rpi_display: add backlight driver and overlay
Add a mailbox-driven backlight controller for the Raspberry Pi DSI
touchscreen display. Requires updated GPU firmware to recognise the
-From ec2e48fda22c57cab56a4332d1a095f91c919493 Mon Sep 17 00:00:00 2001
+From a18791e434387ff2dec3fd8e32d0ae41896d40a5 Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Mon, 16 Nov 2015 14:05:35 +0000
-Subject: [PATCH 088/232] bcm2835-dma: Fix up convert to DMA pool
+Subject: [PATCH 088/304] bcm2835-dma: Fix up convert to DMA pool
---
drivers/dma/bcm2835-dma.c | 36 ++++++++++++++++++++++++++----------
-From 9a67f8f17bb07bbfeee650327c88b6d381ab4af1 Mon Sep 17 00:00:00 2001
+From 8a51551a8e90b0af9ca4d1519e4ab3c4e3f0e672 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 11 Nov 2015 11:38:59 +0000
-Subject: [PATCH 089/232] scripts: Multi-platform support for mkknlimg and
+Subject: [PATCH 089/304] scripts: Multi-platform support for mkknlimg and
knlinfo
The firmware uses tags in the kernel trailer to choose which dtb file
-From 16c40415a78ba028f126b68e2cabf860186ff4f4 Mon Sep 17 00:00:00 2001
+From 1f7a26d3f23eca72e81b23fd2c624975e252b1dc Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 2 Mar 2015 13:01:12 -0800
-Subject: [PATCH 090/232] drm/vc4: Add suport for 3D rendering using the V3D
+Subject: [PATCH 090/304] drm/vc4: Add suport for 3D rendering using the V3D
engine.
This is a squash of the out-of-tree development series. Since that
-From fbec01e2d17b924d91850e17eeecf975e74c9ebf Mon Sep 17 00:00:00 2001
+From 561ea7d6af345cf43a05a188d73f2e9e29a9cde8 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 14 Oct 2015 11:32:14 -0700
-Subject: [PATCH 091/232] drm/vc4: Force HDMI to connected.
+Subject: [PATCH 091/304] drm/vc4: Force HDMI to connected.
For some reason on the downstream tree, the HPD GPIO isn't working.
-From d27b72cbcf572b0e2c18359f494d1f6aa90dd6f3 Mon Sep 17 00:00:00 2001
+From 128c58414e4c53bb5f57330b0928666a14b51f05 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 19 Oct 2015 08:23:18 -0700
-Subject: [PATCH 092/232] drm/vc4: bo cache locking fixes.
+Subject: [PATCH 092/304] drm/vc4: bo cache locking fixes.
Signed-off-by: Eric Anholt <eric@anholt.net>
---
-From 6473779beaeda1017d8487c3f510015f2b9b8f9d Mon Sep 17 00:00:00 2001
+From 6678a113e6eb5104d000f02c8cdc09eec50297ae Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 19 Oct 2015 08:29:41 -0700
-Subject: [PATCH 093/232] drm/vc4: bo cache locking cleanup.
+Subject: [PATCH 093/304] drm/vc4: bo cache locking cleanup.
Signed-off-by: Eric Anholt <eric@anholt.net>
---
-From 1ec9d09f4b9ec69b3b0422fa3c26b3bcc82af64e Mon Sep 17 00:00:00 2001
+From a97d62dbd1d65bcd0bb51aa66b1e928381146cd7 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 19 Oct 2015 08:32:24 -0700
-Subject: [PATCH 094/232] drm/vc4: Use job_lock to protect seqno_cb_list.
+Subject: [PATCH 094/304] drm/vc4: Use job_lock to protect seqno_cb_list.
We're (mostly) not supposed to be using struct_mutex in drivers these
days.
-From 016847d7cd5222d15f9213dc772d3808cd5d6e17 Mon Sep 17 00:00:00 2001
+From fb03ccdfb2baae625f8ab04d4d627dbe97545484 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 19 Oct 2015 08:44:35 -0700
-Subject: [PATCH 095/232] drm/vc4: Drop struct_mutex around CL validation.
+Subject: [PATCH 095/304] drm/vc4: Drop struct_mutex around CL validation.
We were using it so that we could make sure that shader validation
state didn't change while we were validating, but now shader
-From 69aa18660bbe1ee6524c8220beb2af711146bc7f Mon Sep 17 00:00:00 2001
+From ec7429376e7e208e133d1b3fc4b48c45e9fd4826 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 19 Oct 2015 08:44:35 -0700
-Subject: [PATCH 096/232] drm/vc4: Drop struct_mutex around CL validation.
+Subject: [PATCH 096/304] drm/vc4: Drop struct_mutex around CL validation.
We were using it so that we could make sure that shader validation
state didn't change while we were validating, but now shader
-From 111e49bbb002b4dd86ef0c7e0b314c336e6a01c3 Mon Sep 17 00:00:00 2001
+From 61c118e19ca1111715a2b762ff8687039e1daf6e Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 20 Oct 2015 13:59:15 +0100
-Subject: [PATCH 097/232] drm/vc4: Add support for more display plane formats.
+Subject: [PATCH 097/304] drm/vc4: Add support for more display plane formats.
Signed-off-by: Eric Anholt <eric@anholt.net>
---
-From 81dbf19b16cc789162ac94cd4e764a667111386e Mon Sep 17 00:00:00 2001
+From 966f44478d6ccb55bfd20b1249cb20a729519190 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 23 Oct 2015 12:31:56 +0100
-Subject: [PATCH 098/232] drm/vc4: No need to stop the stopped threads.
+Subject: [PATCH 098/304] drm/vc4: No need to stop the stopped threads.
This was leftover debug code from the hackdriver. We never submit
unless the thread is already idle.
-From 9db0b8d54024bf5a2d0c3239aa571d890e8c8b3a Mon Sep 17 00:00:00 2001
+From 7c5a9af8ff8784fa03e51c1db9c00d846edc7cdd Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 23 Oct 2015 12:33:43 +0100
-Subject: [PATCH 099/232] drm/vc4: Remove extra barrier()s aroudn CTnCA/CTnEA
+Subject: [PATCH 099/304] drm/vc4: Remove extra barrier()s aroudn CTnCA/CTnEA
setup.
The writel() that these expand to already does barriers.
-From 03b4b90b8e265158ac3529428f7aaf5f3b0f8a7a Mon Sep 17 00:00:00 2001
+From ef7adf5749220e6d03f2a49ae87e0246990d7318 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 23 Oct 2015 14:57:22 +0100
-Subject: [PATCH 100/232] drm/vc4: Fix a typo in a V3D debug register.
+Subject: [PATCH 100/304] drm/vc4: Fix a typo in a V3D debug register.
Signed-off-by: Eric Anholt <eric@anholt.net>
---
-From a5b0c616e9b40bd7907c5157700661004a8ef331 Mon Sep 17 00:00:00 2001
+From 8797031295e4443ed97e368d7fdfac28a2033c5c Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 2 Nov 2015 17:07:33 +0000
-Subject: [PATCH 101/232] drm/vc4: Enable VC4 modules, and increase CMA size
+Subject: [PATCH 101/304] drm/vc4: Enable VC4 modules, and increase CMA size
with overlay
If using the overlay, be careful not to boot to GUI or run startx,
-From 17f4de0c9daea638476ca0f80123d3523e66fdc0 Mon Sep 17 00:00:00 2001
+From af69b8bba233eadb7ea8efafdcb150e5948a30f4 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 18 Nov 2015 18:29:58 +0000
-Subject: [PATCH 102/232] squash: fixups
+Subject: [PATCH 102/304] squash: fixups
---
drivers/gpu/drm/vc4/Kconfig | 2 +-
-From c1834a750441c3ea55f24377e04cf8d1fb66c877 Mon Sep 17 00:00:00 2001
+From ad6efff00c05f8c62f00bbf40f8d1437d8f9a6c4 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 18 Nov 2015 20:26:03 +0000
-Subject: [PATCH 103/232] squash: add missing vc4-kms-v3d-overlay.dtb to
+Subject: [PATCH 103/304] squash: add missing vc4-kms-v3d-overlay.dtb to
makefile
---
-From 084eeec470e76e8c84cda1a31e323610467913bd Mon Sep 17 00:00:00 2001
+From 6787949088d4c06d784b2c647a13fd9e85c5ea1e Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 12 Oct 2015 11:23:34 -0700
-Subject: [PATCH 104/232] clk: bcm2835: Also build the driver for downstream
+Subject: [PATCH 104/304] clk: bcm2835: Also build the driver for downstream
kernels.
Signed-off-by: Eric Anholt <eric@anholt.net>
-From cbb80e24a9db48390c82c7030cc7f7389aee953f Mon Sep 17 00:00:00 2001
+From bee71d721d6f0269a37a3fab61f9af2b47dc32ca Mon Sep 17 00:00:00 2001
From: Holger Steinhaus <hsteinhaus@gmx.de>
Date: Sat, 14 Nov 2015 18:37:43 +0100
-Subject: [PATCH 105/232] dts: Added overlay for gpio_ir_recv driver
+Subject: [PATCH 105/304] dts: Added overlay for gpio_ir_recv driver
---
arch/arm/boot/dts/overlays/Makefile | 1 +
-From c644d7cae9394e209fc2451b91d2852ebfc85a09 Mon Sep 17 00:00:00 2001
+From a94e2448879eea9ae5344862aa091c3009dec805 Mon Sep 17 00:00:00 2001
From: Alistair Buxton <a.j.buxton@gmail.com>
Date: Sun, 1 Nov 2015 22:27:56 +0000
-Subject: [PATCH 106/232] Build i2c_gpio module and add a device tree overlay
+Subject: [PATCH 106/304] Build i2c_gpio module and add a device tree overlay
to configure it.
---
-From a5a974dbeaaf0be8b1fa5d8c6f117b320ea01b44 Mon Sep 17 00:00:00 2001
+From d8b1f87438596cebc2b8e896c2d1a7c58cb14ca1 Mon Sep 17 00:00:00 2001
From: mwilliams03 <mark.mwilliams@gmail.com>
Date: Sun, 18 Oct 2015 17:07:24 -0700
-Subject: [PATCH 107/232] New overlay for PiScreen2r
+Subject: [PATCH 107/304] New overlay for PiScreen2r
---
arch/arm/boot/dts/overlays/Makefile | 1 +
-From 708f013bf40633883113c3fbaca5555b7d115906 Mon Sep 17 00:00:00 2001
+From c036a8544cdc048ae4fa4370a5899447975184d6 Mon Sep 17 00:00:00 2001
From: Ondrej Wisniewski <ondrej.wisniewski@gmail.com>
Date: Fri, 6 Nov 2015 15:01:28 +0100
-Subject: [PATCH 108/232] dts: Added overlay for Adafruit PiTFT 2.8" capacitive
+Subject: [PATCH 108/304] dts: Added overlay for Adafruit PiTFT 2.8" capacitive
touch screen
---
-From b706bc693765cc80c31076e8fa0e35e798c12bbf Mon Sep 17 00:00:00 2001
+From 249509724dc6c5639d9a1fdea1075b65ba4d5efb Mon Sep 17 00:00:00 2001
From: Stuart MacLean <stuart@hifiberry.com>
Date: Fri, 2 Oct 2015 15:12:59 +0100
-Subject: [PATCH 109/232] Add support for the HiFiBerry DAC+ Pro.
+Subject: [PATCH 109/304] Add support for the HiFiBerry DAC+ Pro.
The HiFiBerry DAC+ and DAC+ Pro products both use the existing bcm sound driver with the DAC+ Pro having a special clock device driver representing the two high precision oscillators.
-From 9fa71fbc6193d214f9a5432f85bb17f47016ba65 Mon Sep 17 00:00:00 2001
+From 09c63075be44e53b139d5741f7397f8e8939ae58 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 5 Oct 2015 10:47:45 +0100
-Subject: [PATCH 110/232] BCM270X_DT: Add at86rf233 overlay
+Subject: [PATCH 110/304] BCM270X_DT: Add at86rf233 overlay
Add an overlay to support the Atmel AT86RF233 WPAN transceiver on spi0.0.
-From 4df259e844e183bf00e1c5eb8ca25dcf19d396ce Mon Sep 17 00:00:00 2001
+From 8f4163a595499ea2950960eb8a1fd187f28e2617 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 18 Dec 2014 16:07:15 -0800
-Subject: [PATCH 111/232] mm: Remove the PFN busy warning
+Subject: [PATCH 111/304] mm: Remove the PFN busy warning
See commit dae803e165a11bc88ca8dbc07a11077caf97bbcb -- the warning is
expected sometimes when using CMA. However, that commit still spams
-From b1891f7b0018e7e778f49c1817692e1f85a1f529 Mon Sep 17 00:00:00 2001
+From 0bd7f965ad98ce1304519379ef72ca1a4960483d Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 19 Nov 2014 12:06:38 -0800
-Subject: [PATCH 112/232] drm: Put an optional field in the driver struct for
+Subject: [PATCH 112/304] drm: Put an optional field in the driver struct for
GEM obj struct size.
This allows a driver to derive from the CMA object without copying all
-From b9e5697fbec13e6203b63649ee5d7c6819a5fb6b Mon Sep 17 00:00:00 2001
+From eb445fa566bd604dd3c0cd5e08e43735ccc149f2 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 30 Oct 2015 10:09:02 -0700
-Subject: [PATCH 113/232] drm/vc4: Add an interface for capturing the GPU state
+Subject: [PATCH 113/304] drm/vc4: Add an interface for capturing the GPU state
after a hang.
This can be parsed with vc4-gpu-tools tools for trying to figure out
-From e4058e84edec652f5a7b3e9e4982eac62b22a90c Mon Sep 17 00:00:00 2001
+From ac832d51da00be28cf70a2c33cfb07ef06a7e94c Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 4 Dec 2015 11:35:34 -0800
-Subject: [PATCH 114/232] drm/vc4: Update a bunch of code to match upstream
+Subject: [PATCH 114/304] drm/vc4: Update a bunch of code to match upstream
submission.
This gets almost everything matching, except for the MSAA support and
-From 659b247a25ea9439be74087726d6adfae7570d12 Mon Sep 17 00:00:00 2001
+From 0625c4c03ba8e37d4757a410018c22b5d549036c Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 11 Dec 2015 19:45:03 -0800
-Subject: [PATCH 115/232] drm: Use the driver's gem_object_free function from
+Subject: [PATCH 115/304] drm: Use the driver's gem_object_free function from
CMA helpers.
VC4 wraps the CMA objects in its own structures, so it needs to do its
-From 878a974dd326f144ba90c1cf018db604bf127835 Mon Sep 17 00:00:00 2001
+From cd77071a812478dd844c4099ddff4022e2ea1ba0 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 17 Jul 2015 13:15:50 -0700
-Subject: [PATCH 116/232] drm/vc4: Add support for MSAA rendering.
+Subject: [PATCH 116/304] drm/vc4: Add support for MSAA rendering.
For MSAA, you set a bit in the binner that halves the size of tiles in
each direction, so you can pack 4 samples per pixel in the tile
-From 6e271c79f63541cbc2e8101a39aa2b0e8d2634c4 Mon Sep 17 00:00:00 2001
+From 5042cf1359c0e6a3d3bf3c16935495dd7de0d0e4 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 8 Dec 2015 14:00:43 -0800
-Subject: [PATCH 117/232] drm/vc4: A few more non-functional changes to sync to
+Subject: [PATCH 117/304] drm/vc4: A few more non-functional changes to sync to
upstream.
At this point all that's left is the force-enable of HDMI connector,
-From 6fa2e872ce528f957b0c3aa735aa46b24ed6601a Mon Sep 17 00:00:00 2001
+From b3d44742ea002847e375285972eaed72e5afcfc6 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 15 Dec 2015 23:46:32 +0000
-Subject: [PATCH 118/232] drm/vc4: Use "hpd-gpios" for HDMI GPIO, like what
+Subject: [PATCH 118/304] drm/vc4: Use "hpd-gpios" for HDMI GPIO, like what
landed upstream.
Signed-off-by: Eric Anholt <eric@anholt.net>
-From 76172185d9852c3e2bf7ace7c040b62dd220d9aa Mon Sep 17 00:00:00 2001
+From 177e3650535f343b34168fa9c0c5af06127336cc Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 7 Dec 2015 12:35:01 -0800
-Subject: [PATCH 119/232] drm/vc4: Synchronize validation code for v2
+Subject: [PATCH 119/304] drm/vc4: Synchronize validation code for v2
submission upstream.
Signed-off-by: Eric Anholt <eric@anholt.net>
-From f825bd28e15f4a4e653f8a81e2a02ac9da1068ca Mon Sep 17 00:00:00 2001
+From ae003608a7caac62858c99e084f47331a6063552 Mon Sep 17 00:00:00 2001
From: janluca <janluca@zedat.fu-berlin.de>
Date: Sun, 27 Dec 2015 14:34:04 +0100
-Subject: [PATCH 120/232] MMC: Do not use mmc_debug if CONFIG_MMC_BCM2835 is
+Subject: [PATCH 120/304] MMC: Do not use mmc_debug if CONFIG_MMC_BCM2835 is
not set
If CONFIG_MMC_BCM2835 was not set the compiling of the kernel failed
-From 127a32cdd6005a42f6b5b63de9d7db573d9de184 Mon Sep 17 00:00:00 2001
+From bc370a3ec1d5f04e1d9db30ffc3e5aff2cee7bd7 Mon Sep 17 00:00:00 2001
From: Devon Fyson <devonfyson@gmail.com>
Date: Wed, 30 Dec 2015 16:40:47 -0500
-Subject: [PATCH 121/232] Extend clock timeout, fix modprobe baudrate
+Subject: [PATCH 121/304] Extend clock timeout, fix modprobe baudrate
parameter.
Set the BSC_CLKT clock streching timeout to 35ms as per SMBus specs.\n- Increase priority of baudrate parameter passed to modprobe (in /etc/modprobe.d/*.conf or command line). Currently custom baudrates don't work because they are overridden by clock-frequency in the platform_device passed to the function.
-From bde59419fd4b9dac732341a62159f01094dfe70d Mon Sep 17 00:00:00 2001
+From 8d1dbb024b39e79f2c7abd1d8c3b13ad6f0296b6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
Date: Thu, 31 Dec 2015 16:44:58 +0100
-Subject: [PATCH 122/232] bcm270x_dt: Add dwc2 and dwc-otg overlays
+Subject: [PATCH 122/304] bcm270x_dt: Add dwc2 and dwc-otg overlays
---
arch/arm/boot/dts/overlays/Makefile | 2 ++
-From 5d03b10c60e70fb5d316706a3777e46dc9dd748e Mon Sep 17 00:00:00 2001
+From f2b8a48896e7f505578083282968c663f7e86acb Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 4 Jan 2016 14:42:17 +0000
-Subject: [PATCH 123/232] BCM270X_DT: Add the sdtweak overlay, for tuning
+Subject: [PATCH 123/304] BCM270X_DT: Add the sdtweak overlay, for tuning
sdhost
The sdhost overlay declares the sdhost interface and allows parameters
-From 17589e37dff9745d9c219973a77031905cb57973 Mon Sep 17 00:00:00 2001
+From 46eadeb2ec2cc6153ee45396dc3c90f85ce79d7e Mon Sep 17 00:00:00 2001
From: Andrew Litt <ajlitt@splunge.net>
Date: Mon, 11 Jan 2016 07:54:21 +0000
-Subject: [PATCH 124/232] bcm2835-mmc: Don't override bus width capabilities
+Subject: [PATCH 124/304] bcm2835-mmc: Don't override bus width capabilities
from devicetree
Take out the force setting of the MMC_CAP_4_BIT_DATA host capability
-From c671b8fada8fe75583e25cd93f9a414c7024e613 Mon Sep 17 00:00:00 2001
+From 99f1bca44186bd6015f93cec4a18594b70a8e0e5 Mon Sep 17 00:00:00 2001
From: Andrew Litt <ajlitt@splunge.net>
Date: Mon, 11 Jan 2016 07:55:54 +0000
-Subject: [PATCH 125/232] SDIO-overlay: add bus_width parameter
+Subject: [PATCH 125/304] SDIO-overlay: add bus_width parameter
Allow setting of the SDIO bus width capability of the bcm2835-mmc
host. This is helpful when only a 1 bit wide bus is connected
-From 688a5f0daa45e0a51b324707768d472e1d715c13 Mon Sep 17 00:00:00 2001
+From e995023b752af4cc6f6863d5beaaf4a3b9144b20 Mon Sep 17 00:00:00 2001
From: wm4 <wm4@nowhere>
Date: Wed, 13 Jan 2016 19:41:45 +0100
-Subject: [PATCH 126/232] bcm2835: extend allowed range of channels and
+Subject: [PATCH 126/304] bcm2835: extend allowed range of channels and
samplerates
Allow everything the videocore accepts.
-From 435962380099cafba4db3d3806b8e03cbcb0774e Mon Sep 17 00:00:00 2001
+From 745dfb0adfc2e3aa4d6c011dd4cb29abeaef8916 Mon Sep 17 00:00:00 2001
From: wm4 <wm4@nowhere>
Date: Wed, 13 Jan 2016 19:42:18 +0100
-Subject: [PATCH 127/232] bcm2835: restrict channels*rate to 8*960000
+Subject: [PATCH 127/304] bcm2835: restrict channels*rate to 8*960000
This is required at least for SPDIF. If the bitrate goes above,
videocore will either resample the audio or corrupt it due to
-From 64fa9f963dffab0145f7960a593422064bb0aa8d Mon Sep 17 00:00:00 2001
+From b94e0945195ad483d345a1d657785d21b85ab246 Mon Sep 17 00:00:00 2001
From: wm4 <wm4@nowhere>
Date: Wed, 13 Jan 2016 19:42:48 +0100
-Subject: [PATCH 128/232] rpi: update vc_vchi_audioserv_defs.h
+Subject: [PATCH 128/304] rpi: update vc_vchi_audioserv_defs.h
Add audioserv 3 extensions. The changes were taken from the paste
linked here:
-From 5efba3f8c180c39609a8d40033ef92046ef0de75 Mon Sep 17 00:00:00 2001
+From eb75f32685cc0bc93053f1acb09e06745d38b60c Mon Sep 17 00:00:00 2001
From: wm4 <wm4@nowhere>
Date: Wed, 13 Jan 2016 19:43:12 +0100
-Subject: [PATCH 129/232] bcm2835: implement channel map API
+Subject: [PATCH 129/304] bcm2835: implement channel map API
Report all layouts supported by the HDMI protocol to userspace.
Make the videocore set the correct layout according to the
-From 26e1f66589860cfcc9a6473d705db890e1b8f6c1 Mon Sep 17 00:00:00 2001
+From fb9b7c60bed82b9a4c6ed329b349e6e5b8a60db9 Mon Sep 17 00:00:00 2001
From: wm4 <wm4@nowhere>
Date: Wed, 13 Jan 2016 19:43:35 +0100
-Subject: [PATCH 130/232] bcm2835: access controls under the audio mutex
+Subject: [PATCH 130/304] bcm2835: access controls under the audio mutex
I don't think the ALSA framework provides any kind of automatic
synchronization within the control callbacks. We most likely need
-From 06931f74092d86087144f070b06a4444df8b444b Mon Sep 17 00:00:00 2001
+From 7223126699f76c76ff770282c5da2395d473014a Mon Sep 17 00:00:00 2001
From: wm4 <wm4@nowhere>
Date: Wed, 13 Jan 2016 19:44:03 +0100
-Subject: [PATCH 131/232] bcm2835: always use 2/4/8 channels for multichannel
+Subject: [PATCH 131/304] bcm2835: always use 2/4/8 channels for multichannel
layouts
Pad the unused channels with NA. This means userspace needs to write
-From 5f7049894f47b3836838cd68e29ee883179c80b3 Mon Sep 17 00:00:00 2001
+From bd016cefc53060ff4c2d00d36be505c263aa3fb3 Mon Sep 17 00:00:00 2001
From: wm4 <wm4@nowhere>
Date: Wed, 13 Jan 2016 19:44:24 +0100
-Subject: [PATCH 132/232] bcm2835: only allow stereo if analogue jack is
+Subject: [PATCH 132/304] bcm2835: only allow stereo if analogue jack is
selected
Sending more than 2 channels to videocore while outputting to analogue
-From 83eca613d0eddd2c8299f114b8fe573ccaffdefc Mon Sep 17 00:00:00 2001
+From 641d7675c007bdf97f10b320fa38d1f089d43d5d Mon Sep 17 00:00:00 2001
From: wm4 <wm4@nowhere>
Date: Wed, 13 Jan 2016 19:44:47 +0100
-Subject: [PATCH 133/232] bcm2835: interpolate audio delay
+Subject: [PATCH 133/304] bcm2835: interpolate audio delay
It appears the GPU only sends us a message all 10ms to update
the playback progress. Other than this, the playback position
-From 22a9a698b6cbce7494ea14dce0e784e098c01ecb Mon Sep 17 00:00:00 2001
+From 48d2aa4f18c8e32198136e5aaea252777cfc0490 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 19 Jan 2016 17:16:38 +0000
-Subject: [PATCH 134/232] bcm2835-sdhost: Add workaround for odd behaviour on
+Subject: [PATCH 134/304] bcm2835-sdhost: Add workaround for odd behaviour on
some cards
For reasons not understood, the sdhost driver fails when reading
-From d038f759d55f39c97e4232851e821b5e4b2fe7a2 Mon Sep 17 00:00:00 2001
+From fad42870d095f811114d6bfd6dedf34595e24a23 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 22 Jan 2016 16:03:24 +0000
-Subject: [PATCH 135/232] bcm2835-sdhost: Add debug_flags dtparam
+Subject: [PATCH 135/304] bcm2835-sdhost: Add debug_flags dtparam
Bit zero disables the single-read-sectors map:
-From 3f4c1f041954c21f9f06c7fe7df3d0e5711667e0 Mon Sep 17 00:00:00 2001
+From 9a7e2ae47f11f7ff5cb4dd2b87e9caeb0953b18d Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 25 Jan 2016 09:12:06 +0000
-Subject: [PATCH 136/232] BCM270X_DT: Add sdio_overclock parameter to sdio
+Subject: [PATCH 136/304] BCM270X_DT: Add sdio_overclock parameter to sdio
overlay
The sdio_overclock parameter is like the overclock_50 parameter, i.e.
-From 6f5d0a941a6a084c677a8843207a42f7b6d5a04d Mon Sep 17 00:00:00 2001
+From c460f1c0adf52314689b3ceb4611a03604ddcbb2 Mon Sep 17 00:00:00 2001
From: Michael Lange <linuxstuff@milaw.biz>
Date: Thu, 21 Jan 2016 18:10:16 +0100
-Subject: [PATCH 137/232] rtc: ds1307: add support for the DT property
+Subject: [PATCH 137/304] rtc: ds1307: add support for the DT property
'wakeup-source'
For RTC chips with no IRQ directly connected to the SoC, the RTC chip
-From 873bf69f1f6bf19f2a0c4cec884cb952b2a19e0c Mon Sep 17 00:00:00 2001
+From 705c8908dc07362e5b0ab975d5842a16cc014e1d Mon Sep 17 00:00:00 2001
From: vitalogy <vitalogy_github@milaw.biz>
Date: Tue, 19 Jan 2016 07:02:02 +0100
-Subject: [PATCH 138/232] dt-overlay: add wittypi-overlay.dts
+Subject: [PATCH 138/304] dt-overlay: add wittypi-overlay.dts
---
arch/arm/boot/dts/overlays/wittypi-overlay.dts | 44 ++++++++++++++++++++++++++
-From c74fc12557305b66537dc6e8ed3ab5d27c507de0 Mon Sep 17 00:00:00 2001
+From 8fc1dbc4b294803d2a6794b1ede681641da45711 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 19 Jan 2016 16:28:05 +0000
-Subject: [PATCH 139/232] FIXUP i2c_bcm2708: Don't change module baudrate
+Subject: [PATCH 139/304] FIXUP i2c_bcm2708: Don't change module baudrate
parameter
Overwriting the baudrate module parameter creates an apparent
-From 4593191b7df9439c295a93250a1f1d68d0938822 Mon Sep 17 00:00:00 2001
+From 796cd923dec66639357bf711ae5758d86e8cd3f3 Mon Sep 17 00:00:00 2001
From: Digital Dreamtime <clive.messer@digitaldreamtime.co.uk>
Date: Thu, 4 Feb 2016 14:14:44 +0000
-Subject: [PATCH 140/232] Allow up to 24dB digital gain to be applied when
+Subject: [PATCH 140/304] Allow up to 24dB digital gain to be applied when
using IQAudIO DAC+
24db_digital_gain DT param can be used to specify that PCM512x
-From 6fda328fc5613d449641ad6701fe8180e70ec338 Mon Sep 17 00:00:00 2001
+From acea17bbc6dd9aabe2da5c95e21b1fc7406cf1fb Mon Sep 17 00:00:00 2001
From: Digital Dreamtime <clive.messer@digitaldreamtime.co.uk>
Date: Thu, 4 Feb 2016 20:04:00 +0000
-Subject: [PATCH 141/232] Limit PCM512x "Digital" gain to 0dB by default with
+Subject: [PATCH 141/304] Limit PCM512x "Digital" gain to 0dB by default with
HiFiBerry DAC+
24db_digital_gain DT param can be used to specify that PCM512x
-From 1b3fd5b03546474795b7557a04c7c3c5cf162ecb Mon Sep 17 00:00:00 2001
+From 1bf407348eb9be0b793da4350f2daba91db4ea4f Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 8 Feb 2016 09:46:33 +0000
-Subject: [PATCH 142/232] BCM270X_DT: Adjust overlay README formatting
+Subject: [PATCH 142/304] BCM270X_DT: Adjust overlay README formatting
---
arch/arm/boot/dts/overlays/README | 414 +++++++++++++++++++-------------------
-From 60425f3b85682fa3378cb6aeecce15a50384b7e2 Mon Sep 17 00:00:00 2001
+From 978d4ec47c4a66491140e964939889c427feee64 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Thu, 11 Feb 2016 16:51:01 +0000
-Subject: [PATCH 144/232] bcm2835-sdhost: Major revision
+Subject: [PATCH 143/304] bcm2835-sdhost: Major revision
This is a significant revision of the bcm2835-sdhost driver. It
improves on the original in a number of ways:
-From 177ef127e03243ede5b1b00032d5f9fdce94673b Mon Sep 17 00:00:00 2001
+From 5920a56447c13b86d073a388be113c28c2a8681d Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 12 Feb 2016 15:38:00 +0000
-Subject: [PATCH 145/232] BCM270X_DT: Add dtparams for the SD interface
+Subject: [PATCH 144/304] BCM270X_DT: Add dtparams for the SD interface
Add new base dtparams sd_overclock, sd_force_pio, sd_pio_limit
and sd_debug.
-From 63ff907f6e6ab3b93535dc2b5251b7b41eaf7ec2 Mon Sep 17 00:00:00 2001
+From 9b47d7a9a98af616d910ed6ee561afa39fc41855 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Fri, 12 Feb 2016 14:50:25 +0000
-Subject: [PATCH 146/232] dcw_otg: trim xfer length when buffer larger than
+Subject: [PATCH 145/304] dcw_otg: trim xfer length when buffer larger than
allocated size is received
---
-From ebb44753d0310c6adb03a9b448a4038c3e37e6e0 Mon Sep 17 00:00:00 2001
+From 1bb1322d03193dc4214b030afad507d0df18e55c Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 15 Feb 2016 10:00:27 +0000
-Subject: [PATCH 147/232] bcm2835-sdhost: Restore ATOMIC flag to PIO sg mapping
+Subject: [PATCH 146/304] bcm2835-sdhost: Restore ATOMIC flag to PIO sg mapping
Allocation problems have been seen in a wireless driver, and
this is the only change which might have been responsible.
-From 55e8519aa4c86b37f1933e8e53c6e97372d61871 Mon Sep 17 00:00:00 2001
+From b94760d282632d4542f5b0fa785b8213311b1484 Mon Sep 17 00:00:00 2001
From: Craig Roberts <cjr@craigroberts.net>
Date: Tue, 16 Feb 2016 10:03:42 +0000
-Subject: [PATCH 148/232] Updated smsc95xx driver to check for a valid MAC
+Subject: [PATCH 147/304] Updated smsc95xx driver to check for a valid MAC
address in eeprom before using smsc95xx.macaddr parameter passed on command
line.
-From 3f4cd273dcc578b48783a23fb2cbef50e7fd151d Mon Sep 17 00:00:00 2001
+From 1e2926e39764ae4642df940fa799657c204399a9 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 17 Feb 2016 19:02:31 +0000
-Subject: [PATCH 149/232] dcw_otg: Make trimming messages less noisy
+Subject: [PATCH 148/304] dcw_otg: Make trimming messages less noisy
---
drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 6 ++++--
-From f7f0e8b831ae66fc19c1f9457975d0f8b31ea601 Mon Sep 17 00:00:00 2001
+From 4d033ce157ae8cce859a038c47aa955d4a5c37cd Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Thu, 18 Feb 2016 15:28:14 +0000
-Subject: [PATCH 150/232] BCM270X_DT: at86rf233 overlay - drop to 3MHz
+Subject: [PATCH 149/304] BCM270X_DT: at86rf233 overlay - drop to 3MHz
The consensus is that 6MHz is too fast, but that 3MHz is OK.
-From 76667f779c11557d7ebc84130619c25f3c1642af Mon Sep 17 00:00:00 2001
+From 9d6ac53072ccc9bc93cd5698b62220cf4900a198 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 19 Feb 2016 12:04:48 +0000
-Subject: [PATCH 151/232] bcm2835-sdhost: Downgrade log message status
+Subject: [PATCH 150/304] bcm2835-sdhost: Downgrade log message status
---
drivers/mmc/host/bcm2835-sdhost.c | 4 ++--
-From ab8cd307467682fa1df2bfadeb3ac88c086f861c Mon Sep 17 00:00:00 2001
+From ad3ed29f3c3e945a82602cd3623ac53d1cba1999 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 15 Jan 2016 16:48:27 +0000
-Subject: [PATCH 152/232] config: Enable HCI over UARTs
+Subject: [PATCH 151/304] config: Enable HCI over UARTs
---
arch/arm/configs/bcm2709_defconfig | 3 +++
-From 85dc4378167d99218df01bb0512a4def9710a0a5 Mon Sep 17 00:00:00 2001
+From d01147893a87ead6e3f129a36f61bcdf34fc588a Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Thu, 17 Dec 2015 13:37:07 +0000
-Subject: [PATCH 153/232] hci_h5: Don't send conf_req when ACTIVE
+Subject: [PATCH 152/304] hci_h5: Don't send conf_req when ACTIVE
Without this patch, a modem and kernel can continuously bombard each
other with conf_req and conf_rsp messages, in a demented game of tag.
-From e9950fa4e93333baad36537cc46121cc7cecf455 Mon Sep 17 00:00:00 2001
+From d06dacf300fbd1eee8c8b1e9c916f4856622b9c2 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 23 Feb 2016 17:26:48 +0000
-Subject: [PATCH 154/232] amba_pl011: Don't use DT aliases for numbering
+Subject: [PATCH 153/304] amba_pl011: Don't use DT aliases for numbering
The pl011 driver looks for DT aliases of the form "serial<n>",
and if found uses <n> as the device ID. This can cause
-From 0316ebbf545738333e188197d196b618c17b171e Mon Sep 17 00:00:00 2001
+From c866120163103778042130f37cc436e1512030ce Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 15 Dec 2015 15:35:57 -0800
-Subject: [PATCH 155/232] clk: bcm2835: Add bindings for the auxiliary
+Subject: [PATCH 154/304] clk: bcm2835: Add bindings for the auxiliary
peripheral clock gates.
These will be used for enabling UART1, SPI1, and SPI2.
-From cfe1737d9aab03ecd152291df704606a7724eb21 Mon Sep 17 00:00:00 2001
+From 7da110b37747778f802371f41cd1eabc0859354e Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 15 Dec 2015 15:35:58 -0800
-Subject: [PATCH 156/232] clk: bcm2835: Add a driver for the auxiliary
+Subject: [PATCH 155/304] clk: bcm2835: Add a driver for the auxiliary
peripheral clock gates.
There are a pair of SPI masters and a mini UART that were last minute
-From 2cf8e02af4645b90aa63f8cdbd0cb4403e2bee8f Mon Sep 17 00:00:00 2001
+From b2c4fc29ec059ff82f6f82a2192146aff696a8ef Mon Sep 17 00:00:00 2001
From: Fraser <github@frasersdev.net>
Date: Tue, 23 Feb 2016 10:04:37 +1100
-Subject: [PATCH 157/232] Aux SPI 1&2 implementation
+Subject: [PATCH 156/304] Aux SPI 1&2 implementation
Adds aux spi 1 & 2 devices to compatible raspberry PIs.
* Minor config of the driver build environment to ensure they get built
-From 29c79ce79c70db703a4621ecc7d24208ca991981 Mon Sep 17 00:00:00 2001
+From 3231b20a0e3b20458c443a0ab91045869cbea06a Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Tue, 23 Feb 2016 17:28:23 +0100
-Subject: [PATCH 158/232] ASoC: bcm: add missing .owner fields in sound card
+Subject: [PATCH 157/304] ASoC: bcm: add missing .owner fields in sound card
drivers
If snd_soc_card.owner is not set the kernel won't do usage refcounting
-From edd0a6e9b22c8edad94b9e8a6ca370912fbeb642 Mon Sep 17 00:00:00 2001
+From 6c5578bc1a55f862aaac3ad6e1826a0de32f4734 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Wed, 20 Jan 2016 17:50:09 +0000
-Subject: [PATCH 159/232] smsx95xx: Add option to disable the crimes against
+Subject: [PATCH 158/304] smsx95xx: Add option to disable the crimes against
truesize fix
It may improve iperf numbers on Pi 1, but may generate dmesg warnings and possibly cause network issues
-From e1024a4269e314d45522f24b0ac86c77675e7909 Mon Sep 17 00:00:00 2001
+From 46aa468ca952060fd0f45e7da5b79f656b9d1dc0 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Tue, 23 Feb 2016 19:56:04 +0000
-Subject: [PATCH 160/232] bcm2835-virtgpio: Virtual GPIO driver
+Subject: [PATCH 159/304] bcm2835-virtgpio: Virtual GPIO driver
Add a virtual GPIO driver that uses the firmware mailbox interface to
request that the VPU toggles LEDs.
-From 4aa902b37606ca425a2d1dedd400347b11a0e61d Mon Sep 17 00:00:00 2001
+From 043927e5556d65b6e40d21a0b53bca06aa9b2d43 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Thu, 21 Jan 2016 17:57:49 +0000
-Subject: [PATCH 161/232] BCM270X_DT: Add Pi3 support
+Subject: [PATCH 160/304] BCM270X_DT: Add Pi3 support
---
arch/arm/boot/dts/Makefile | 1 +
-From 6014b99c7f39813c76b51e940677219c7dd41041 Mon Sep 17 00:00:00 2001
+From 2d787b8c422a777f688b185420268dc618d995e4 Mon Sep 17 00:00:00 2001
From: Dave Stevenson <6by9@users.noreply.github.com>
Date: Mon, 8 Feb 2016 23:49:41 +0000
-Subject: [PATCH 162/232] DT: Add overlays to configure I2C pins
+Subject: [PATCH 161/304] DT: Add overlays to configure I2C pins
Lifted from
https://www.raspberrypi.org/forums/viewtopic.php?f=107&t=120938&p=825883
-From f22f155684481bb96748677bc58705d27bf4f06b Mon Sep 17 00:00:00 2001
+From 52697652d41b7947e2ed1c45a954f426a4135441 Mon Sep 17 00:00:00 2001
From: Dhiraj Goel <dhiraj.goel@gmail.com>
Date: Thu, 3 Mar 2016 21:10:50 -0800
-Subject: [PATCH 163/232] bcm2835-camera: fix a bug in computation of frame
+Subject: [PATCH 162/304] bcm2835-camera: fix a bug in computation of frame
timestamp
Fixes #1318
-From 1807dd78b1af8eff8976f3431e4bf98dccd2113d Mon Sep 17 00:00:00 2001
+From 235eb2e7b520269614b4a91d15d22eef7923a4fb Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 2 Mar 2016 10:59:05 +0000
-Subject: [PATCH 164/232] BCM270X_DT: Add pi3-disable-bt overlay
+Subject: [PATCH 163/304] BCM270X_DT: Add pi3-disable-bt overlay
Disable Bluetooth and restore UART0/ttyAMA0 over GPIOs 14 & 15. To disable
the systemd service that initialises the modem so it doesn't use the UART:
-From 4adf0d94785a304b51f8205ecade7bc97b26a00b Mon Sep 17 00:00:00 2001
+From fd6395774b0b0adfafcb3ef11c5055f85e8896dd Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 7 Mar 2016 09:53:03 +0000
-Subject: [PATCH 165/232] BCM270X_DT: Add pi3-miniuart-bt DT overlay
+Subject: [PATCH 164/304] BCM270X_DT: Add pi3-miniuart-bt DT overlay
Switch Pi3 Bluetooth function to use the mini-UART (ttyS0) and restore
UART0/ttyAMA0 over GPIOs 14 & 15. Note that this may reduce the maximum
-From 2efc547c5e535a2061312e63a459cdee9635cdf9 Mon Sep 17 00:00:00 2001
+From 3d4b13cc4a0dbea19ba73d9a0c7e785e1d963d55 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 7 Mar 2016 13:38:39 +0000
-Subject: [PATCH 166/232] Pi3 DT: Add dtparams for the SD interface
+Subject: [PATCH 165/304] Pi3 DT: Add dtparams for the SD interface
Add new base dtparams sd_overclock, sd_force_pio, sd_pio_limit
and sd_debug. These were missed out of the initial Pi3 DTB.
-From 68c89607e3451adc83a158e99a582be85f047465 Mon Sep 17 00:00:00 2001
+From 9a9ac626fd93632c3bacf9f61b758262d98a260c Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 7 Mar 2016 15:05:11 +0000
-Subject: [PATCH 167/232] vchiq_arm: Tweak the logging output
+Subject: [PATCH 166/304] vchiq_arm: Tweak the logging output
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From 1131510a589ae7262b8861af8d2f4a000710d59c Mon Sep 17 00:00:00 2001
+From d6b47c6dc22a1fbe2fcb5c742936a32baad60409 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 7 Mar 2016 16:46:39 +0000
-Subject: [PATCH 168/232] bcm2835-sdhost: Only claim one DMA channel
+Subject: [PATCH 167/304] bcm2835-sdhost: Only claim one DMA channel
With both MMC controllers enabled there are few DMA channels left. The
bcm2835-sdhost driver only uses DMA in one direction at a time, so it
-From ea4b1c5c2ddbb6caba43ab9b0103542a4ca7e1f0 Mon Sep 17 00:00:00 2001
+From ade651419c0a60756b12bde37270de3aaede1545 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 8 Mar 2016 09:49:16 +0000
-Subject: [PATCH 169/232] bcm2835-mmc: Only claim one DMA channel
+Subject: [PATCH 168/304] bcm2835-mmc: Only claim one DMA channel
With both MMC controllers enabled there are few DMA channels left. The
bcm2835-mmc driver only uses DMA in one direction at a time, so it
-From 83428789f8b11c2caf2b85998db0f0874cd3e896 Mon Sep 17 00:00:00 2001
+From 1054095c79084b44a5245ff2d8fc38aa82d1afd8 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Tue, 8 Mar 2016 17:08:39 +0000
-Subject: [PATCH 170/232] config: rebuild with savedefconfig
+Subject: [PATCH 169/304] config: rebuild with savedefconfig
---
arch/arm/configs/bcm2709_defconfig | 3 +--
-From b704288cc9104b018bebf77528f9ff74b6c355a4 Mon Sep 17 00:00:00 2001
+From c7834c34977089c45c3614ce531142258f088eee Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Tue, 8 Mar 2016 17:06:33 +0000
-Subject: [PATCH 171/232] config: Add module for mcp3422 ADC
+Subject: [PATCH 170/304] config: Add module for mcp3422 ADC
---
arch/arm/configs/bcm2709_defconfig | 1 +
-From a25355e1fe4284b87170bec5d2ee77f90a62602c Mon Sep 17 00:00:00 2001
+From 9a54d9b11416f92d09656f342d3d7ae495876dcd Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 8 Mar 2016 16:18:57 +0000
-Subject: [PATCH 172/232] Pi3 DT: Add pull-ups on the UART RX lines
+Subject: [PATCH 171/304] Pi3 DT: Add pull-ups on the UART RX lines
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From 209d0307ba01e0f15f5e75bc77d8edaa51aa91ab Mon Sep 17 00:00:00 2001
+From 67c1b07aca518f756140a682d0e6fe383e293515 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 9 Mar 2016 21:28:52 +0000
-Subject: [PATCH 174/232] BCM270X_DT: rpi-display overlay - add swapxy param
+Subject: [PATCH 173/304] BCM270X_DT: rpi-display overlay - add swapxy param
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From eb4d55c34018bbb92808264217a0b2857d2b2ae6 Mon Sep 17 00:00:00 2001
+From db1f9419a8d30e9a861ac63889f0b7845c3310f1 Mon Sep 17 00:00:00 2001
From: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
Date: Fri, 11 Mar 2016 11:44:35 +0000
-Subject: [PATCH 175/232] Remove I2S config from bt_pins.
+Subject: [PATCH 174/304] Remove I2S config from bt_pins.
Remove I2S config from bt_pins. Causes issues with clock alignment when I2S is
used by an external DAC via GPIO header.
-From fa95cd11c54c77d6151b7588b1f41457d8775c60 Mon Sep 17 00:00:00 2001
+From de37d281502aff4e4a88872cf0a6ef5e36b7484d Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 10 Aug 2015 09:44:59 +0100
-Subject: [PATCH 176/232] Revert "scripts/dtc: Add overlay support"
+Subject: [PATCH 175/304] Revert "scripts/dtc: Add overlay support"
This reverts commit fa6d1755c2fdd9451077d8248e3804f0619f19b9.
---
-From 8ed747466ab2fac41d870582b149385d3e8c2d43 Mon Sep 17 00:00:00 2001
+From 8560a09e578580fa46d649e5b15a3779968007f6 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 10 Aug 2015 09:49:15 +0100
-Subject: [PATCH 177/232] scripts/dtc: Update to upstream version 1.4.1
+Subject: [PATCH 176/304] scripts/dtc: Update to upstream version 1.4.1
Includes the new localfixups format.
-From 7499c16ca9e47899ff65070af57588a8f541f707 Mon Sep 17 00:00:00 2001
+From 28059745722d31f48971035bbca98d689adb41f6 Mon Sep 17 00:00:00 2001
From: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Date: Thu, 22 Oct 2015 23:30:04 +0300
-Subject: [PATCH 178/232] configfs: implement binary attributes
+Subject: [PATCH 177/304] configfs: implement binary attributes
ConfigFS lacked binary attributes up until now. This patch
introduces support for binary attributes in a somewhat similar
-From 54ca6e08ce89f5e33de78db7deff727c12513397 Mon Sep 17 00:00:00 2001
+From 46852dc03df7e271cedafb6405ab3b47fa57fc1f Mon Sep 17 00:00:00 2001
From: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Date: Wed, 3 Dec 2014 13:23:28 +0200
-Subject: [PATCH 179/232] OF: DT-Overlay configfs interface
+Subject: [PATCH 178/304] OF: DT-Overlay configfs interface
This is a port of Pantelis Antoniou's v3 port that makes use of the
new upstreamed configfs support for binary attributes.
-From c841449374b2acd024ae8971bbd2474c6ba27309 Mon Sep 17 00:00:00 2001
+From 3006a98a1fe05d8a9ed22c5ffa3387bcffd3e6e7 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 13 Mar 2015 12:43:36 +0000
-Subject: [PATCH 180/232] Protect __release_resource against resources without
+Subject: [PATCH 179/304] Protect __release_resource against resources without
parents
Without this patch, removing a device tree overlay can crash here.
-From 420e1b8c5cec3bbccd4c260ff836a71e54df084e Mon Sep 17 00:00:00 2001
+From 37896fb199519698fe090107f60013158738ea4a Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 13 Mar 2015 20:00:21 +0000
-Subject: [PATCH 181/232] BCM270X_DT: Add a .dtbo target, use for overlays
+Subject: [PATCH 180/304] BCM270X_DT: Add a .dtbo target, use for overlays
Change the filenames and extensions to keep the pre-DDT style of
overlay (<name>-overlay.dtb) distinct from new ones that use a
-From e56b2ead4021e94eb15f8dd7240c607fe61ce57f Mon Sep 17 00:00:00 2001
+From c5a86acf2f24c46c59eb5290c45cee0893b6bbb9 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 29 May 2015 11:18:58 +0100
-Subject: [PATCH 182/232] scripts/knlinfo: Decode DDTK atom
+Subject: [PATCH 181/304] scripts/knlinfo: Decode DDTK atom
Show the DDTK atom as being a boolean.
-From aa7d45428dba9267190fa17a424db693628856f6 Mon Sep 17 00:00:00 2001
+From e942b566a2a1d3b104fcbaa1af2613bae32ed80a Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 29 May 2015 11:48:59 +0100
-Subject: [PATCH 183/232] Enable Dynamic Device Tree for bcmrpi_defconfig and
+Subject: [PATCH 182/304] Enable Dynamic Device Tree for bcmrpi_defconfig and
bcm2709_defconfig
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
-From 293a0e05a554b39c3d3587f0631c495485ec903b Mon Sep 17 00:00:00 2001
+From 5db216e0816c390542f813c0b3f6fbcc1c4e63c8 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Sun, 13 Mar 2016 16:14:44 +0000
-Subject: [PATCH 184/232] SQUASH: Add CONFIG_OF_CONFIGFS to bcmrpi_defconfig
+Subject: [PATCH 183/304] SQUASH: Add CONFIG_OF_CONFIGFS to bcmrpi_defconfig
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From e948b371fbb724b7d715dee41c0db5ef5a028a13 Mon Sep 17 00:00:00 2001
+From 987d8a609678ea5c04664d02adb1f408e5b62a8b Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 14 Mar 2016 16:56:54 +0000
-Subject: [PATCH 185/232] dts, kbuild: dtbs_install installs .dtbo files too
+Subject: [PATCH 184/304] dts, kbuild: dtbs_install installs .dtbo files too
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From c215c0d855343400b53ae2ec8b015a3f4a3eb27e Mon Sep 17 00:00:00 2001
+From 8a55d01fb0245d518898960123c3cb1b96dd9080 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 15 Mar 2016 14:10:29 +0000
-Subject: [PATCH 186/232] bcm2835-sdhost: Workaround for "slow" sectors
+Subject: [PATCH 185/304] bcm2835-sdhost: Workaround for "slow" sectors
Some cards have been seen to cause timeouts after certain sectors are
read. This workaround enforces a minimum delay between the stop after
-From 605effb19bd81578339b66e642ff5e5d4f86babd Mon Sep 17 00:00:00 2001
+From 7066f3b1bf7ddf5bf68815e8a53bef8ecf8e0e52 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 15 Mar 2016 15:49:16 +0000
-Subject: [PATCH 187/232] BCM270X_DT: Add labels to spidev nodes
+Subject: [PATCH 186/304] BCM270X_DT: Add labels to spidev nodes
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From 666d717a56639ca89b6bba18a325b1c530683fac Mon Sep 17 00:00:00 2001
+From 33de40886f08899a438a12e26c50d0e6d025775e Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 15 Mar 2016 16:27:26 +0000
-Subject: [PATCH 188/232] BCM270X_DT: Use spidev labels in overlays
+Subject: [PATCH 187/304] BCM270X_DT: Use spidev labels in overlays
---
arch/arm/boot/dts/overlays/ads7846-overlay.dts | 22 ++++++++++-------
-From 3259cf06132d0987314a37f39b0b18750b127eba Mon Sep 17 00:00:00 2001
+From fd1aeca317a5c84e700ca5198e8759e9063661a6 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 15 Mar 2016 16:41:37 +0000
-Subject: [PATCH 189/232] BCM270X_DT: Build and document the wittypi overlay
+Subject: [PATCH 188/304] BCM270X_DT: Build and document the wittypi overlay
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From cd57bc1baa3d03746b6bf78996cbd46460558c28 Mon Sep 17 00:00:00 2001
+From 438d786eb8499167a46ca9736e470d1943d272b8 Mon Sep 17 00:00:00 2001
From: Matthias Reichl <hias@horus.com>
Date: Tue, 15 Mar 2016 21:13:39 +0100
-Subject: [PATCH 190/232] scripts/dtc: Fix UMR causing corrupt dtbo overlay
+Subject: [PATCH 189/304] scripts/dtc: Fix UMR causing corrupt dtbo overlay
files
struct fixup_entry is allocated from the heap but it's member
-From d171758951c497d0cd557040884ffb4efd231c3c Mon Sep 17 00:00:00 2001
+From 061113506e00c7a93a98c6b50c6a811e6dfe329b Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 16 Mar 2016 08:35:06 +0000
-Subject: [PATCH 191/232] BCM270X_DT: Add dtparam for uart1
+Subject: [PATCH 190/304] BCM270X_DT: Add dtparam for uart1
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From 916634f9a59abd7f0de793ac5b523a89c882dbdf Mon Sep 17 00:00:00 2001
+From 2c9f391fa4dd8b666fe66ba961b29bd2b0a645d5 Mon Sep 17 00:00:00 2001
From: Przemek Rudy <prudy1@o2.pl>
Date: Fri, 11 Mar 2016 22:41:26 +0100
-Subject: [PATCH 192/232] dwc-overlay: Use label so overrides can apply.
+Subject: [PATCH 191/304] dwc-overlay: Use label so overrides can apply.
---
arch/arm/boot/dts/overlays/dwc2-overlay.dts | 10 +++++-----
-From b30fecff47b19f93b4d20706bc6c6e6c0b972344 Mon Sep 17 00:00:00 2001
+From 1b6ead4b4b409136e21beed9b2c51ce71b348cf6 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 22 Jan 2016 13:06:39 -0800
-Subject: [PATCH 193/232] drm/vc4: Add a debugfs node for tracking execution
+Subject: [PATCH 192/304] drm/vc4: Add a debugfs node for tracking execution
state.
Signed-off-by: Eric Anholt <eric@anholt.net>
-From 64da292638fcacae979a5e8b3239969ec4275eb9 Mon Sep 17 00:00:00 2001
+From 072d5f91f60b8732af5c3529cbad1cad0eda798f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 25 Jan 2016 13:03:33 -0800
-Subject: [PATCH 194/232] drm/vc4: Include vc4_drm.h in uapi in downstream
+Subject: [PATCH 193/304] drm/vc4: Include vc4_drm.h in uapi in downstream
build.
Signed-off-by: Eric Anholt <eric@anholt.net>
-From 4b02ed240cad8575c197d01d083a10e398f768bd Mon Sep 17 00:00:00 2001
+From 12ddf64c85deb1d1261bdde36c128cd1a178a4d7 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 25 Jan 2016 13:05:00 -0800
-Subject: [PATCH 195/232] drm/vc4: Validate that WAIT_BO padding is cleared.
+Subject: [PATCH 194/304] drm/vc4: Validate that WAIT_BO padding is cleared.
This is ABI future-proofing if we ever want to extend the pad to mean
something.
-From 7ff02c91259682b40b5ce8a90f114925d71572c0 Mon Sep 17 00:00:00 2001
+From 0361731aa4eddac6e10bad6aa0386bb10ae7c221 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 25 Jan 2016 13:52:41 -0800
-Subject: [PATCH 196/232] drm/vc4: Fix the clear color for the first tile
+Subject: [PATCH 195/304] drm/vc4: Fix the clear color for the first tile
rendered.
Apparently in hardware (as opposed to simulation), the clear colors
-From d6211c47e6671faf74389dbcbe29454c5997defb Mon Sep 17 00:00:00 2001
+From f832d2e9a9b142e2bf7ab5de8154aa6f992651a0 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 25 Jan 2016 14:13:12 -0800
-Subject: [PATCH 197/232] drm/vc4: Return an ERR_PTR from BO creation instead
+Subject: [PATCH 196/304] drm/vc4: Return an ERR_PTR from BO creation instead
of NULL.
Fixes igt vc4_create_bo/create-bo-0 by returning -EINVAL from the
-From 39e77e9d67511ac9bfbb00ab471fc7b0374dcdf6 Mon Sep 17 00:00:00 2001
+From 516e9685df7152891b08710c8722cbfe5257b8b9 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 25 Jan 2016 14:32:41 -0800
-Subject: [PATCH 198/232] drm/vc4: Fix -ERESTARTSYS error return from BO waits.
+Subject: [PATCH 197/304] drm/vc4: Fix -ERESTARTSYS error return from BO waits.
This caused the wait ioctls to claim that waiting had completed when
we actually got interrupted by a signal before it was done. Fixes
-From a9221f160c28301850d5368d283c751b18950f2a Mon Sep 17 00:00:00 2001
+From ed499ca6841fc64d564d100cb31b30aba9b4d40f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 25 Jan 2016 14:33:50 -0800
-Subject: [PATCH 199/232] drm/vc4: Drop error message on seqno wait timeouts.
+Subject: [PATCH 198/304] drm/vc4: Drop error message on seqno wait timeouts.
These ioctls end up getting exposed to userspace, and having normal
user requests print DRM errors is obviously wrong. The message was
-From 19d839cafdd5ddb1233df5be821d702e655d2d16 Mon Sep 17 00:00:00 2001
+From 5304c73254ae50ae4dbd06938e5d594516742930 Mon Sep 17 00:00:00 2001
From: campag <dave-lowe@ntlworld.com>
Date: Wed, 24 Feb 2016 16:45:42 +0000
-Subject: [PATCH 200/232] BCM270X_DT: Add 1-bit SDIO using minimal pins...
+Subject: [PATCH 199/304] BCM270X_DT: Add 1-bit SDIO using minimal pins...
... for that mode: GPIOs 22-25.
---
-From 76d3e26b821b2490619f4762b5f604e77636fdb1 Mon Sep 17 00:00:00 2001
+From b23b33abf4487eb6008994f3cf5a3f39841add70 Mon Sep 17 00:00:00 2001
From: Michael Heimpold <michael.heimpold@i2se.com>
Date: Fri, 29 Jan 2016 12:00:37 +0100
-Subject: [PATCH 202/232] Add overlay and enable support for QCA7000 board
+Subject: [PATCH 201/304] Add overlay and enable support for QCA7000 board
This adds a device tree overlay for the QCA7000 which can be used
when attaching an I2SE's PLC Stamp micro EVK to the Raspberry Pi.
-From c9276ae7cfecbd1df477ff31116682e72dd6d8f7 Mon Sep 17 00:00:00 2001
+From abd2da573a492fe1c64fa7a269b121046b2f3acf Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 9 Mar 2016 13:28:24 +0000
-Subject: [PATCH 203/232] serial: Take care starting a hung-up tty's port
+Subject: [PATCH 202/304] serial: Take care starting a hung-up tty's port
tty_port_hangup sets a port's tty field to NULL (holding the port lock),
but uart_tx_stopped, called from __uart_start (with the port lock),
-From b7bbcabcce3f31bca25f17d68fb9eb0e2e045184 Mon Sep 17 00:00:00 2001
+From 067bdb295322ba1ba0288e36a8e5db0935f384c1 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Thu, 17 Mar 2016 10:16:16 +0000
-Subject: [PATCH 204/232] pi3-miniuart-bt-overlay: Correct and clarify info
+Subject: [PATCH 203/304] pi3-miniuart-bt-overlay: Correct and clarify info
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From 05a2610389127e4cfcc2b9afdec83e1176b205bc Mon Sep 17 00:00:00 2001
+From cbce83f2cade68b80c6004e97135d37728d9c30f Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Thu, 17 Mar 2016 10:41:56 +0000
-Subject: [PATCH 205/232] pwm overlays: Params must have in-overlay targets
+Subject: [PATCH 204/304] pwm overlays: Params must have in-overlay targets
---
arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts | 9 ++++++++-
-From 985c06bd528e49fd44155c3da0c6107c46d947cc Mon Sep 17 00:00:00 2001
+From 5c6d93ef128041a46ceb25a3c458a60405e9c60d Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Fri, 18 Mar 2016 13:06:29 +0000
-Subject: [PATCH 206/232] BCM270X_DT: Switch Compute Module to MMC
+Subject: [PATCH 205/304] BCM270X_DT: Switch Compute Module to MMC
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From 4558f488edf41daddd4bceed975f3af8cee89033 Mon Sep 17 00:00:00 2001
+From d23d96422dd69238fa10d24ecb0323427359ef30 Mon Sep 17 00:00:00 2001
From: P33M <P33M@github.com>
Date: Fri, 18 Mar 2016 17:38:37 +0000
-Subject: [PATCH 207/232] dwc_otg: Don't free qh align buffers in atomic
+Subject: [PATCH 206/304] dwc_otg: Don't free qh align buffers in atomic
context
---
-From 7956536a3d78ba0ef8ec990651b315664ed70f90 Mon Sep 17 00:00:00 2001
+From cd141372388a05c228ce0552cfc6edc3bf3b65d6 Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Mon, 21 Mar 2016 15:38:38 +0000
-Subject: [PATCH 208/232] dwc_otg: Enable the hack for Split Interrupt
+Subject: [PATCH 207/304] dwc_otg: Enable the hack for Split Interrupt
transactions by default
dwc_otg.fiq_fsm_mask=0xF has long been a suggestion for users with audio stutters or other USB bandwidth issues.
-From adc10c5da2b83bbc8c893e3a745b43890f27e2ac Mon Sep 17 00:00:00 2001
+From f26e0311778ed510125e3d83ebf22109dc986835 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Sat, 19 Mar 2016 16:51:37 +0000
-Subject: [PATCH 209/232] BCM270X_DT: Remove explicit claiming of UART pins
+Subject: [PATCH 208/304] BCM270X_DT: Remove explicit claiming of UART pins
It is convenient to be able to map a different function to the UART
pins (e.g. DPI for vga666) without having to disable the UART first.
-From 79e3ee1d325bf1aea9e255127dd132265b734efe Mon Sep 17 00:00:00 2001
+From da94c9df9e9b77422bdecfb2af64a8c10061d206 Mon Sep 17 00:00:00 2001
From: Rodrigo Freire <rfreire@rf.usersys.redhat.com>
Date: Tue, 22 Mar 2016 12:40:33 -0300
-Subject: [PATCH 210/232] lirc_rpi: Lower IR reception error to debug
+Subject: [PATCH 209/304] lirc_rpi: Lower IR reception error to debug
Lowers a IR reception error condition message to KERNEL_DEBUG
---
-From 26eb219f0645eb9848887ca25c0a073a9a40d852 Mon Sep 17 00:00:00 2001
+From 397f801c082178a6df9ca198d2143f2f4bd0a275 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 23 Mar 2016 14:16:25 +0000
-Subject: [PATCH 211/232] vchiq_arm: Access the dequeue_pending flag locked
+Subject: [PATCH 210/304] vchiq_arm: Access the dequeue_pending flag locked
Reading through this code looking for another problem (now found in userland)
the use of dequeue_pending outside a lock didn't seem safe.
-From 10cd986960d2ad1fd881fa3338af40e612076ba4 Mon Sep 17 00:00:00 2001
+From 500de79a1d1785b7d7b189897412ce17f3c34869 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 23 Mar 2016 15:57:14 +0000
-Subject: [PATCH 212/232] BCM270X_DT: Add pi3-act-led overlay
+Subject: [PATCH 211/304] BCM270X_DT: Add pi3-act-led overlay
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From 2faaa2ccef9e4c595bd26f14285c225ceea6097e Mon Sep 17 00:00:00 2001
+From 523feff6ae02ad31e7d35aa07685ea1d37eae9f1 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 23 Mar 2016 20:53:47 +0000
-Subject: [PATCH 213/232] vchiq_arm: Service callbacks must not fail
+Subject: [PATCH 212/304] vchiq_arm: Service callbacks must not fail
Service callbacks are not allowed to return an error. The internal callback
that delivers events and messages to user tasks does not enqueue them if
-From 09e64d48934eb812bab8667dcce81d0387092644 Mon Sep 17 00:00:00 2001
+From 031f69058a890ac8df5834cde9e0f6301b9a75d3 Mon Sep 17 00:00:00 2001
From: Dave Stevenson <6by9@users.noreply.github.com>
Date: Thu, 17 Mar 2016 18:16:16 +0000
-Subject: [PATCH 214/232] Add configs and overlay for PCA9548 I2C mux
+Subject: [PATCH 213/304] Add configs and overlay for PCA9548 I2C mux
Adds kernel configs for I2C muxes and a dt overlay for PCA9548
that adds the 8 muxed I2C buses and mux device.
-From 6ec2115ccc87288132b345ab2cd05aed2d3beb97 Mon Sep 17 00:00:00 2001
+From b36d418b125935c8dcdb51b129fb3ec4c0e2658c Mon Sep 17 00:00:00 2001
From: Nicolas Boullis <nboullis@debian.org>
Date: Wed, 23 Mar 2016 23:40:15 +0100
-Subject: [PATCH 215/232] BCM270X_DT: Add DS1339 to i2c-rtc overlay
+Subject: [PATCH 214/304] BCM270X_DT: Add DS1339 to i2c-rtc overlay
---
arch/arm/boot/dts/overlays/README | 4 ++++
-From a160443a0d967ea6394cd0d1b7a0ab8ef2da3ff1 Mon Sep 17 00:00:00 2001
+From 250a9cb281e520a1c22ff9dd86d2fb44fddb4fe9 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Tue, 29 Mar 2016 15:32:30 +0100
-Subject: [PATCH 216/232] copy_from_user: CPU_SW_DOMAIN_PAN compatibility
+Subject: [PATCH 215/304] copy_from_user: CPU_SW_DOMAIN_PAN compatibility
The downstream copy_from_user acceleration must also play nice with
CONFIG_CPU_SW_DOMAIN_PAN.
-From 4b89d07fd299a0f4e25321920cb74416ba2e638e Mon Sep 17 00:00:00 2001
+From 13a986c782983be4fcc2c780dd73bfd428cc82b3 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 30 Mar 2016 16:33:09 +0100
-Subject: [PATCH 217/232] bcm2835-sdhost: Adjust to core clock changes
+Subject: [PATCH 216/304] bcm2835-sdhost: Adjust to core clock changes
The SDHOST block uses the core clock, so previously it has been
necessary to prevent the core clock from changing in order to maintain
-From 73f4b796019a7e9b7314851657aebd5f92f3ff75 Mon Sep 17 00:00:00 2001
+From 83d447c00bc185c49b621aebc850abab989c96ef Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 30 Mar 2016 17:07:15 +0100
-Subject: [PATCH 218/232] BCM270X_DT: Document hazards of sdhost overlay
+Subject: [PATCH 217/304] BCM270X_DT: Document hazards of sdhost overlay
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
-From 2af1218a8a0220fec526f64d03977b8451afb4c8 Mon Sep 17 00:00:00 2001
+From 65d0fed05912509d60d94fdba8debe1a095c73a6 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 30 Mar 2016 17:23:15 +0100
-Subject: [PATCH 219/232] cpufreq: Temporarily ignore io_is_busy=1
+Subject: [PATCH 218/304] cpufreq: Temporarily ignore io_is_busy=1
To speed testing of the new sdhost driver that adapts to changes in
core_freq, hack the on-demand governor to treat io_is_busy=1 as
-From c353af0f83220068c10f6593b1767576b9b6cc18 Mon Sep 17 00:00:00 2001
+From c486342fb4b09f5d676a213cdf7e366b72e528f3 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Wed, 30 Mar 2016 20:18:38 +0100
-Subject: [PATCH 220/232] Revert "cpufreq: Temporarily ignore io_is_busy=1"
+Subject: [PATCH 219/304] Revert "cpufreq: Temporarily ignore io_is_busy=1"
This reverts commit 2af1218a8a0220fec526f64d03977b8451afb4c8.
---
-From a436f21ba8e57517734c24d2b571d5aed888be36 Mon Sep 17 00:00:00 2001
+From 645e1a7bb2e9ab5d3a12fd8eac7b553ee8122ba9 Mon Sep 17 00:00:00 2001
From: Daniel Borkmann <daniel@iogearbox.net>
Date: Thu, 7 Jan 2016 15:50:22 +0100
-Subject: [PATCH 221/232] net, sched: add skb_at_tc_ingress helper
+Subject: [PATCH 220/304] net, sched: add skb_at_tc_ingress helper
Add a skb_at_tc_ingress() as this will be needed elsewhere as well and
can hide the ugly ifdef.
-From 20260462773366a5734e5268dae0a4c179a21a2d Mon Sep 17 00:00:00 2001
+From d2b23892c9f7b04b68280889bea7823ba555b325 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Thu, 31 Mar 2016 15:44:53 +0100
-Subject: [PATCH 224/232] bcm2835-sdhost: Precalc divisors and overclocks
+Subject: [PATCH 222/304] bcm2835-sdhost: Precalc divisors and overclocks
Recalculating the clock divisors when the core clock changes is wasteful
and makes it harder to manage the overclock settings. Instead,
-From 9524a87ecce1788c8f77d2b86deee65d11b4190d Mon Sep 17 00:00:00 2001
+From 829cedfe9323ee329b031ac23efd913a586ae7bb Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 4 Apr 2016 12:35:32 +0100
-Subject: [PATCH 225/232] Revert "bcm2835-sdhost: Precalc divisors and
+Subject: [PATCH 223/304] Revert "bcm2835-sdhost: Precalc divisors and
overclocks"
This reverts commit 20260462773366a5734e5268dae0a4c179a21a2d.
-From 28035a98dc9820c065dc64ad3016a1f71a9911f2 Mon Sep 17 00:00:00 2001
+From bfe59970666dc1035c2cf79967de51df9ecf734a Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 4 Apr 2016 12:35:51 +0100
-Subject: [PATCH 226/232] Revert "bcm2835-sdhost: Adjust to core clock changes"
+Subject: [PATCH 224/304] Revert "bcm2835-sdhost: Adjust to core clock changes"
This reverts commit 4b89d07fd299a0f4e25321920cb74416ba2e638e.
---
-From 08532d242d7702ae0add95096aa49c5e96e066e2 Mon Sep 17 00:00:00 2001
+From c249254c1a0195566538a15dbfe2459da2f16643 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.org>
Date: Mon, 4 Apr 2016 16:03:18 +0100
-Subject: [PATCH 227/232] bcm2835-sdhost: Firmware manages the clock divisor
+Subject: [PATCH 225/304] bcm2835-sdhost: Firmware manages the clock divisor
The bcm2835-sdhost driver hands control of the CDIV clock divisor
register to matching firmware, allowing it to adjust to a changing
-From 9f0a3f09ec2d80fed2781b341527ae6bd5666cd8 Mon Sep 17 00:00:00 2001
+From 274a8e5251c2c12345b3069a3539ff27b220cb2a Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Mon, 4 Apr 2016 19:52:27 +0100
-Subject: [PATCH 228/232] Revert "Revert "cpufreq: Temporarily ignore
+Subject: [PATCH 226/304] Revert "Revert "cpufreq: Temporarily ignore
io_is_busy=1""
This reverts commit c353af0f83220068c10f6593b1767576b9b6cc18.
-From ed825c0f1cfce352d446f33ef7f798134b8d6cb6 Mon Sep 17 00:00:00 2001
+From acf428e77480d8c4fa0f13959fd347e45e7b2d1a Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Thu, 31 Mar 2016 16:49:52 +0100
-Subject: [PATCH 229/232] config: Enabled IPV6_SUBTREES
+Subject: [PATCH 227/304] config: Enabled IPV6_SUBTREES
---
arch/arm/configs/bcm2709_defconfig | 1 +
-From 3cea4c3fef10a33547949610d9a81ac9950b5be9 Mon Sep 17 00:00:00 2001
+From e27f96aeb0f516b87a284993951c2366ef24914d Mon Sep 17 00:00:00 2001
From: Sam Nazarko <email@samnazarko.co.uk>
Date: Fri, 1 Apr 2016 17:27:21 +0100
-Subject: [PATCH 230/232] add smsc95xx packetsize module_param
+Subject: [PATCH 228/304] add smsc95xx packetsize module_param
Signed-off-by: Sam Nazarko <email@samnazarko.co.uk>
---
-From 3ce05d6e2e4994e06ec73ff95969ae189681a8e8 Mon Sep 17 00:00:00 2001
+From 45746412917e5d7f8298a6642788c9487737e25a Mon Sep 17 00:00:00 2001
From: popcornmix <popcornmix@gmail.com>
Date: Tue, 5 Apr 2016 19:40:12 +0100
-Subject: [PATCH 231/232] reboot: Use power off rather than busy spinning when
+Subject: [PATCH 229/304] reboot: Use power off rather than busy spinning when
halt is requested
---
-From ccb9ab7ba94d7b005f4fd820f1cb91caf73dbf89 Mon Sep 17 00:00:00 2001
+From 893c530176f330b10ada8d8468788020bb8e2070 Mon Sep 17 00:00:00 2001
From: HiassofT <github@hias.horus.com>
Date: Wed, 6 Apr 2016 21:45:01 +0200
-Subject: [PATCH 232/232] Revert "bcm2835-dma: Fix dreq not set for slave
+Subject: [PATCH 230/304] Revert "bcm2835-dma: Fix dreq not set for slave
transfers"
This reverts commit 8ad957e866a1fe1450f663f2b00a57d7de44904c.
--- /dev/null
+From 6273867fcddb010a62be4d1d5dcba124b1661681 Mon Sep 17 00:00:00 2001
+From: Dave Stevenson <6by9@users.noreply.github.com>
+Date: Fri, 1 Apr 2016 15:28:46 +0100
+Subject: [PATCH 231/304] RPi config: Add CONFIG_PWM_PCA9685 for NXP PCA9685
+ driver over I2C
+
+Includes DT overlay to configure it.
+
+Signed-off-by: Dave Stevenson <6by9@users.noreply.github.com>
+---
+ arch/arm/boot/dts/overlays/Makefile | 1 +
+ arch/arm/boot/dts/overlays/README | 6 +++++
+ .../boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts | 26 ++++++++++++++++++++++
+ arch/arm/configs/bcm2709_defconfig | 1 +
+ arch/arm/configs/bcmrpi_defconfig | 1 +
+ 5 files changed, 35 insertions(+)
+ create mode 100644 arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts
+
+--- a/arch/arm/boot/dts/overlays/Makefile
++++ b/arch/arm/boot/dts/overlays/Makefile
+@@ -30,6 +30,7 @@ dtbo-$(RPI_DT_OVERLAYS) += hy28b.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += i2c-rtc.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += i2c-gpio.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += i2c-mux-pca9548a.dtbo
++dtbo-$(RPI_DT_OVERLAYS) += i2c-pwm-pca9685a.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += i2c0-bcm2708.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += i2c1-bcm2708.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += i2s-mmap.dtbo
+--- a/arch/arm/boot/dts/overlays/README
++++ b/arch/arm/boot/dts/overlays/README
+@@ -366,6 +366,12 @@ Load: dtoverlay=i2c-mux-pca9548a,<para
+ Params: addr I2C address of PCA9548A (default 0x70)
+
+
++Name: i2c-pwm-pca9685a
++Info: Adds support for an NXP PCA9685A I2C PWM controller on i2c_arm
++Load: dtoverlay=i2c-pwm-pca9685a,<param>=<val>
++Params: addr I2C address of PCA9685A (default 0x40)
++
++
+ Name: i2c-rtc
+ Info: Adds support for a number of I2C Real Time Clock devices
+ Load: dtoverlay=i2c-rtc,<param>=<val>
+--- /dev/null
++++ b/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts
+@@ -0,0 +1,26 @@
++// Definitions for NXP PCA9685A I2C PWM controller on ARM I2C bus.
++/dts-v1/;
++/plugin/;
++
++/{
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&i2c_arm>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ pca: pca@40 {
++ compatible = "nxp,pca9685";
++ #pwm-cells = <2>;
++ reg = <0x40>;
++ status = "okay";
++ };
++ };
++ };
++ __overrides__ {
++ addr = <&pca>,"reg:0";
++ };
++};
+--- a/arch/arm/configs/bcm2709_defconfig
++++ b/arch/arm/configs/bcm2709_defconfig
+@@ -1122,6 +1122,7 @@ CONFIG_MCP320X=m
+ CONFIG_MCP3422=m
+ CONFIG_DHT11=m
+ CONFIG_PWM_BCM2835=m
++CONFIG_PWM_PCA9685=m
+ CONFIG_RASPBERRYPI_FIRMWARE=y
+ CONFIG_EXT4_FS=y
+ CONFIG_EXT4_FS_POSIX_ACL=y
+--- a/arch/arm/configs/bcmrpi_defconfig
++++ b/arch/arm/configs/bcmrpi_defconfig
+@@ -1129,6 +1129,7 @@ CONFIG_MCP320X=m
+ CONFIG_MCP3422=m
+ CONFIG_DHT11=m
+ CONFIG_PWM_BCM2835=m
++CONFIG_PWM_PCA9685=m
+ CONFIG_RASPBERRYPI_FIRMWARE=y
+ CONFIG_EXT4_FS=y
+ CONFIG_EXT4_FS_POSIX_ACL=y
--- /dev/null
+From 6d33c5dd29d06ef631215ccf48d02592b227e103 Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Fri, 8 Apr 2016 17:43:27 +0100
+Subject: [PATCH 232/304] BCM270X_DT: Don't generate "linux,phandle" props
+
+The EPAPR standard says to use "phandle" properties to store phandles,
+rather than the deprecated "linux,phandle" version. By default, dtc
+generates both, but adding "-H epapr" causes it to only generate
+"phandle"s, saving some space and clutter.
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ arch/arm/boot/dts/Makefile | 2 +-
+ scripts/Makefile.lib | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -813,5 +813,5 @@ clean-files := *.dtb
+
+ # Enable fixups to support overlays on BCM2708 platforms
+ ifeq ($(RPI_DT_OVERLAYS),y)
+- DTC_FLAGS ?= -@
++ DTC_FLAGS ?= -@ -H epapr
+ endif
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -294,7 +294,7 @@ $(obj)/%.dtb: $(src)/%.dts FORCE
+
+ quiet_cmd_dtco = DTCO $@
+ cmd_dtco = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
+- $(objtree)/scripts/dtc/dtc -@ -O dtb -o $@ -b 0 \
++ $(objtree)/scripts/dtc/dtc -@ -H epapr -O dtb -o $@ -b 0 \
+ -i $(dir $<) $(DTC_FLAGS) \
+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
--- /dev/null
+From 12b8bcf4d6d4a188ad2bcbae564f32fba4166f71 Mon Sep 17 00:00:00 2001
+From: 6by9 <6by9@users.noreply.github.com>
+Date: Fri, 8 Apr 2016 18:15:43 +0100
+Subject: [PATCH 233/304] V4L2 driver updates (#1393)
+
+* BCM2835-V4L2: Correct ISO control and add V4L2_CID_ISO_SENSITIVITY_AUTO
+
+https://github.com/raspberrypi/linux/issues/1251
+
+V4L2_CID_ISO_SENSITIVITY was not advertising ISO*1000 as it should.
+V4L2_CID_ISO_SENSITIVITY_AUTO was not implemented, so was taking
+V4L2_CID_ISO_SENSITIVITY as 0 for auto mode.
+Still accepts 0 for auto, but also abides by the new parameter.
+
+Signed-off-by: Dave Stevenson <6by9@users.noreply.github.com>
+
+* BCM2835-V4L2: Add a video_nr parameter.
+
+Adds a kernel parameter "video_nr" to specify the preferred
+/dev/videoX device node.
+https://www.raspberrypi.org/forums/viewtopic.php?f=38&t=136120&p=905545
+
+Signed-off-by: Dave Stevenson <6by9@users.noreply.github.com>
+
+* BCM2835-V4L2: Add support for multiple cameras
+
+Ask GPU on load how many cameras have been detected, and
+enumerate that number of devices.
+Only applicable on the Compute Module as no other device
+exposes multiple CSI2 interfaces.
+
+Signed-off-by: Dave Stevenson <6by9@users.noreply.github.com>
+
+* BCM2835-V4L2: Add control of the overlay location and alpha.
+
+Actually do something useful in vidioc_s_fmt_vid_overlay and
+vidioc_try_fmt_vid_overlay, rather than effectively having
+read-only fields.
+
+Signed-off-by: Dave Stevenson <6by9@users.noreply.github.com>
+
+* BCM2835-V4L2: V4L2-Compliance failure fix
+
+VIDIOC_TRY_FMT was failing due to bytesperline not
+being set correctly by default.
+
+Signed-off-by: Dave Stevenson <6by9@users.noreply.github.com>
+
+* BCM2835-V4L2: Make all module parameters static
+
+Clean up to correct variable scope
+
+Signed-off-by: Dave Stevenson <6by9@users.noreply.github.com>
+---
+ drivers/media/platform/bcm2835/bcm2835-camera.c | 372 +++++++++++++++--------
+ drivers/media/platform/bcm2835/bcm2835-camera.h | 19 +-
+ drivers/media/platform/bcm2835/controls.c | 31 +-
+ drivers/media/platform/bcm2835/mmal-parameters.h | 33 ++
+ 4 files changed, 320 insertions(+), 135 deletions(-)
+
+--- a/drivers/media/platform/bcm2835/bcm2835-camera.c
++++ b/drivers/media/platform/bcm2835/bcm2835-camera.c
+@@ -45,6 +45,8 @@
+ #define MAX_VIDEO_MODE_WIDTH 1280
+ #define MAX_VIDEO_MODE_HEIGHT 720
+
++#define MAX_BCM2835_CAMERAS 2
++
+ MODULE_DESCRIPTION("Broadcom 2835 MMAL video capture");
+ MODULE_AUTHOR("Vincent Sanders");
+ MODULE_LICENSE("GPL");
+@@ -54,8 +56,13 @@ int bcm2835_v4l2_debug;
+ module_param_named(debug, bcm2835_v4l2_debug, int, 0644);
+ MODULE_PARM_DESC(bcm2835_v4l2_debug, "Debug level 0-2");
+
+-int max_video_width = MAX_VIDEO_MODE_WIDTH;
+-int max_video_height = MAX_VIDEO_MODE_HEIGHT;
++#define UNSET (-1)
++static int video_nr[] = {[0 ... (MAX_BCM2835_CAMERAS - 1)] = UNSET };
++module_param_array(video_nr, int, NULL, 0644);
++MODULE_PARM_DESC(video_nr, "videoX start numbers, -1 is autodetect");
++
++static int max_video_width = MAX_VIDEO_MODE_WIDTH;
++static int max_video_height = MAX_VIDEO_MODE_HEIGHT;
+ module_param(max_video_width, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
+ MODULE_PARM_DESC(max_video_width, "Threshold for video mode");
+ module_param(max_video_height, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
+@@ -70,11 +77,12 @@ MODULE_PARM_DESC(max_video_height, "Thre
+ * our function table list (actually switch to an alternate set, but same
+ * result).
+ */
+-int gst_v4l2src_is_broken = 0;
++static int gst_v4l2src_is_broken;
+ module_param(gst_v4l2src_is_broken, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
+ MODULE_PARM_DESC(gst_v4l2src_is_broken, "If non-zero, enable workaround for Gstreamer");
+
+-static struct bm2835_mmal_dev *gdev; /* global device data */
++/* global device data array */
++static struct bm2835_mmal_dev *gdev[MAX_BCM2835_CAMERAS];
+
+ #define FPS_MIN 1
+ #define FPS_MAX 90
+@@ -413,6 +421,17 @@ static int enable_camera(struct bm2835_m
+ {
+ int ret;
+ if (!dev->camera_use_count) {
++ ret = vchiq_mmal_port_parameter_set(
++ dev->instance,
++ &dev->component[MMAL_COMPONENT_CAMERA]->control,
++ MMAL_PARAMETER_CAMERA_NUM, &dev->camera_num,
++ sizeof(dev->camera_num));
++ if (ret < 0) {
++ v4l2_err(&dev->v4l2_dev,
++ "Failed setting camera num, ret %d\n", ret);
++ return -EINVAL;
++ }
++
+ ret = vchiq_mmal_component_enable(
+ dev->instance,
+ dev->component[MMAL_COMPONENT_CAMERA]);
+@@ -647,6 +666,30 @@ static struct vb2_ops bm2835_mmal_video_
+ IOCTL operations
+ ------------------------------------------------------------------*/
+
++static int set_overlay_params(struct bm2835_mmal_dev *dev,
++ struct vchiq_mmal_port *port)
++{
++ int ret;
++ struct mmal_parameter_displayregion prev_config = {
++ .set = MMAL_DISPLAY_SET_LAYER | MMAL_DISPLAY_SET_ALPHA |
++ MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN,
++ .layer = PREVIEW_LAYER,
++ .alpha = dev->overlay.global_alpha,
++ .fullscreen = 0,
++ .dest_rect = {
++ .x = dev->overlay.w.left,
++ .y = dev->overlay.w.top,
++ .width = dev->overlay.w.width,
++ .height = dev->overlay.w.height,
++ },
++ };
++ ret = vchiq_mmal_port_parameter_set(dev->instance, port,
++ MMAL_PARAMETER_DISPLAYREGION,
++ &prev_config, sizeof(prev_config));
++
++ return ret;
++}
++
+ /* overlay ioctl */
+ static int vidioc_enum_fmt_vid_overlay(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+@@ -678,10 +721,31 @@ static int vidioc_g_fmt_vid_overlay(stru
+ static int vidioc_try_fmt_vid_overlay(struct file *file, void *priv,
+ struct v4l2_format *f)
+ {
+- /* Only support one format so get the current one. */
+- vidioc_g_fmt_vid_overlay(file, priv, f);
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
+
+- /* todo: allow the size and/or offset to be changed. */
++ f->fmt.win.field = V4L2_FIELD_NONE;
++ f->fmt.win.chromakey = 0;
++ f->fmt.win.clips = NULL;
++ f->fmt.win.clipcount = 0;
++ f->fmt.win.bitmap = NULL;
++
++ v4l_bound_align_image(&f->fmt.win.w.width, MIN_WIDTH, MAX_WIDTH, 1,
++ &f->fmt.win.w.height, MIN_HEIGHT, MAX_HEIGHT,
++ 1, 0);
++ v4l_bound_align_image(&f->fmt.win.w.left, MIN_WIDTH, MAX_WIDTH, 1,
++ &f->fmt.win.w.top, MIN_HEIGHT, MAX_HEIGHT,
++ 1, 0);
++
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "Overlay: Now w/h %dx%d l/t %dx%d\n",
++ f->fmt.win.w.width, f->fmt.win.w.height,
++ f->fmt.win.w.left, f->fmt.win.w.top);
++
++ v4l2_dump_win_format(1,
++ bcm2835_v4l2_debug,
++ &dev->v4l2_dev,
++ &f->fmt.win,
++ __func__);
+ return 0;
+ }
+
+@@ -693,8 +757,11 @@ static int vidioc_s_fmt_vid_overlay(stru
+ vidioc_try_fmt_vid_overlay(file, priv, f);
+
+ dev->overlay = f->fmt.win;
++ if (dev->component[MMAL_COMPONENT_PREVIEW]->enabled) {
++ set_overlay_params(dev,
++ &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]);
++ }
+
+- /* todo: program the preview port parameters */
+ return 0;
+ }
+
+@@ -704,20 +771,6 @@ static int vidioc_overlay(struct file *f
+ struct bm2835_mmal_dev *dev = video_drvdata(file);
+ struct vchiq_mmal_port *src;
+ struct vchiq_mmal_port *dst;
+- struct mmal_parameter_displayregion prev_config = {
+- .set = MMAL_DISPLAY_SET_LAYER | MMAL_DISPLAY_SET_ALPHA |
+- MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN,
+- .layer = PREVIEW_LAYER,
+- .alpha = 255,
+- .fullscreen = 0,
+- .dest_rect = {
+- .x = dev->overlay.w.left,
+- .y = dev->overlay.w.top,
+- .width = dev->overlay.w.width,
+- .height = dev->overlay.w.height,
+- },
+- };
+-
+ if ((on && dev->component[MMAL_COMPONENT_PREVIEW]->enabled) ||
+ (!on && !dev->component[MMAL_COMPONENT_PREVIEW]->enabled))
+ return 0; /* already in requested state */
+@@ -749,9 +802,7 @@ static int vidioc_overlay(struct file *f
+ if (ret < 0)
+ goto error;
+
+- ret = vchiq_mmal_port_parameter_set(dev->instance, dst,
+- MMAL_PARAMETER_DISPLAYREGION,
+- &prev_config, sizeof(prev_config));
++ ret = set_overlay_params(dev, dst);
+ if (ret < 0)
+ goto error;
+
+@@ -782,6 +833,9 @@ static int vidioc_g_fbuf(struct file *fi
+ struct vchiq_mmal_port *preview_port =
+ &dev->component[MMAL_COMPONENT_CAMERA]->
+ output[MMAL_CAMERA_PORT_PREVIEW];
++
++ a->capability = V4L2_FBUF_CAP_EXTERNOVERLAY |
++ V4L2_FBUF_CAP_GLOBAL_ALPHA;
+ a->flags = V4L2_FBUF_FLAG_OVERLAY;
+ a->fmt.width = preview_port->es.video.width;
+ a->fmt.height = preview_port->es.video.height;
+@@ -1445,6 +1499,34 @@ static struct video_device vdev_template
+ .release = video_device_release_empty,
+ };
+
++static int get_num_cameras(struct vchiq_mmal_instance *instance)
++{
++ int ret;
++ struct vchiq_mmal_component *cam_info_component;
++ struct mmal_parameter_camera_info_t cam_info = {0};
++ int param_size = sizeof(cam_info);
++
++ /* create a camera_info component */
++ ret = vchiq_mmal_component_init(instance, "camera_info",
++ &cam_info_component);
++ if (ret < 0)
++ /* Unusual failure - let's guess one camera. */
++ return 1;
++
++ if (vchiq_mmal_port_parameter_get(instance,
++ &cam_info_component->control,
++ MMAL_PARAMETER_CAMERA_INFO,
++ &cam_info,
++ ¶m_size)) {
++ pr_info("Failed to get camera info\n");
++ }
++
++ vchiq_mmal_component_finalise(instance,
++ cam_info_component);
++
++ return cam_info.num_cameras;
++}
++
+ static int set_camera_parameters(struct vchiq_mmal_instance *instance,
+ struct vchiq_mmal_component *camera)
+ {
+@@ -1685,7 +1767,9 @@ static int __init bm2835_mmal_init_devic
+ /* video device needs to be able to access instance data */
+ video_set_drvdata(vfd, dev);
+
+- ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
++ ret = video_register_device(vfd,
++ VFL_TYPE_GRABBER,
++ video_nr[dev->camera_num]);
+ if (ret < 0)
+ return ret;
+
+@@ -1696,10 +1780,52 @@ static int __init bm2835_mmal_init_devic
+ return 0;
+ }
+
++void bcm2835_cleanup_instance(struct bm2835_mmal_dev *dev)
++{
++ if (!dev)
++ return;
++
++ v4l2_info(&dev->v4l2_dev, "unregistering %s\n",
++ video_device_node_name(&dev->vdev));
++
++ video_unregister_device(&dev->vdev);
++
++ if (dev->capture.encode_component) {
++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
++ "mmal_exit - disconnect tunnel\n");
++ vchiq_mmal_port_connect_tunnel(dev->instance,
++ dev->capture.camera_port, NULL);
++ vchiq_mmal_component_disable(dev->instance,
++ dev->capture.encode_component);
++ }
++ vchiq_mmal_component_disable(dev->instance,
++ dev->component[MMAL_COMPONENT_CAMERA]);
++
++ vchiq_mmal_component_finalise(dev->instance,
++ dev->
++ component[MMAL_COMPONENT_VIDEO_ENCODE]);
++
++ vchiq_mmal_component_finalise(dev->instance,
++ dev->
++ component[MMAL_COMPONENT_IMAGE_ENCODE]);
++
++ vchiq_mmal_component_finalise(dev->instance,
++ dev->component[MMAL_COMPONENT_PREVIEW]);
++
++ vchiq_mmal_component_finalise(dev->instance,
++ dev->component[MMAL_COMPONENT_CAMERA]);
++
++ v4l2_ctrl_handler_free(&dev->ctrl_handler);
++
++ v4l2_device_unregister(&dev->v4l2_dev);
++
++ kfree(dev);
++}
++
+ static struct v4l2_format default_v4l2_format = {
+ .fmt.pix.pixelformat = V4L2_PIX_FMT_JPEG,
+ .fmt.pix.width = 1024,
+- .fmt.pix.bytesperline = 1024,
++ .fmt.pix.bytesperline = 0,
+ .fmt.pix.height = 768,
+ .fmt.pix.sizeimage = 1024*768,
+ };
+@@ -1709,76 +1835,93 @@ static int __init bm2835_mmal_init(void)
+ int ret;
+ struct bm2835_mmal_dev *dev;
+ struct vb2_queue *q;
++ int camera;
++ unsigned int num_cameras;
++ struct vchiq_mmal_instance *instance;
+
+- dev = kzalloc(sizeof(*gdev), GFP_KERNEL);
+- if (!dev)
+- return -ENOMEM;
+-
+- /* setup device defaults */
+- dev->overlay.w.left = 150;
+- dev->overlay.w.top = 50;
+- dev->overlay.w.width = 1024;
+- dev->overlay.w.height = 768;
+- dev->overlay.clipcount = 0;
+- dev->overlay.field = V4L2_FIELD_NONE;
+-
+- dev->capture.fmt = &formats[3]; /* JPEG */
+-
+- /* v4l device registration */
+- snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name),
+- "%s", BM2835_MMAL_MODULE_NAME);
+- ret = v4l2_device_register(NULL, &dev->v4l2_dev);
+- if (ret)
+- goto free_dev;
+-
+- /* setup v4l controls */
+- ret = bm2835_mmal_init_controls(dev, &dev->ctrl_handler);
+- if (ret < 0)
+- goto unreg_dev;
+- dev->v4l2_dev.ctrl_handler = &dev->ctrl_handler;
+-
+- /* mmal init */
+- ret = mmal_init(dev);
++ ret = vchiq_mmal_init(&instance);
+ if (ret < 0)
+- goto unreg_dev;
++ return ret;
+
+- /* initialize queue */
+- q = &dev->capture.vb_vidq;
+- memset(q, 0, sizeof(*q));
+- q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+- q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ;
+- q->drv_priv = dev;
+- q->buf_struct_size = sizeof(struct mmal_buffer);
+- q->ops = &bm2835_mmal_video_qops;
+- q->mem_ops = &vb2_vmalloc_memops;
+- q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+- ret = vb2_queue_init(q);
+- if (ret < 0)
+- goto unreg_dev;
++ num_cameras = get_num_cameras(instance);
++ if (num_cameras > MAX_BCM2835_CAMERAS)
++ num_cameras = MAX_BCM2835_CAMERAS;
++
++ for (camera = 0; camera < num_cameras; camera++) {
++ dev = kzalloc(sizeof(struct bm2835_mmal_dev), GFP_KERNEL);
++ if (!dev)
++ return -ENOMEM;
++
++ dev->camera_num = camera;
++
++ /* setup device defaults */
++ dev->overlay.w.left = 150;
++ dev->overlay.w.top = 50;
++ dev->overlay.w.width = 1024;
++ dev->overlay.w.height = 768;
++ dev->overlay.clipcount = 0;
++ dev->overlay.field = V4L2_FIELD_NONE;
++ dev->overlay.global_alpha = 255;
++
++ dev->capture.fmt = &formats[3]; /* JPEG */
++
++ /* v4l device registration */
++ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name),
++ "%s", BM2835_MMAL_MODULE_NAME);
++ ret = v4l2_device_register(NULL, &dev->v4l2_dev);
++ if (ret)
++ goto free_dev;
+
+- /* v4l2 core mutex used to protect all fops and v4l2 ioctls. */
+- mutex_init(&dev->mutex);
++ /* setup v4l controls */
++ ret = bm2835_mmal_init_controls(dev, &dev->ctrl_handler);
++ if (ret < 0)
++ goto unreg_dev;
++ dev->v4l2_dev.ctrl_handler = &dev->ctrl_handler;
++
++ /* mmal init */
++ dev->instance = instance;
++ ret = mmal_init(dev);
++ if (ret < 0)
++ goto unreg_dev;
++
++ /* initialize queue */
++ q = &dev->capture.vb_vidq;
++ memset(q, 0, sizeof(*q));
++ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ;
++ q->drv_priv = dev;
++ q->buf_struct_size = sizeof(struct mmal_buffer);
++ q->ops = &bm2835_mmal_video_qops;
++ q->mem_ops = &vb2_vmalloc_memops;
++ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++ ret = vb2_queue_init(q);
++ if (ret < 0)
++ goto unreg_dev;
++
++ /* v4l2 core mutex used to protect all fops and v4l2 ioctls. */
++ mutex_init(&dev->mutex);
++
++ /* initialise video devices */
++ ret = bm2835_mmal_init_device(dev, &dev->vdev);
++ if (ret < 0)
++ goto unreg_dev;
++
++ /* Really want to call vidioc_s_fmt_vid_cap with the default
++ * format, but currently the APIs don't join up.
++ */
++ ret = mmal_setup_components(dev, &default_v4l2_format);
++ if (ret < 0) {
++ v4l2_err(&dev->v4l2_dev,
++ "%s: could not setup components\n", __func__);
++ goto unreg_dev;
++ }
+
+- /* initialise video devices */
+- ret = bm2835_mmal_init_device(dev, &dev->vdev);
+- if (ret < 0)
+- goto unreg_dev;
++ v4l2_info(&dev->v4l2_dev,
++ "Broadcom 2835 MMAL video capture ver %s loaded.\n",
++ BM2835_MMAL_VERSION);
+
+- /* Really want to call vidioc_s_fmt_vid_cap with the default
+- * format, but currently the APIs don't join up.
+- */
+- ret = mmal_setup_components(dev, &default_v4l2_format);
+- if (ret < 0) {
+- v4l2_err(&dev->v4l2_dev,
+- "%s: could not setup components\n", __func__);
+- goto unreg_dev;
++ gdev[camera] = dev;
+ }
+-
+- v4l2_info(&dev->v4l2_dev,
+- "Broadcom 2835 MMAL video capture ver %s loaded.\n",
+- BM2835_MMAL_VERSION);
+-
+- gdev = dev;
+ return 0;
+
+ unreg_dev:
+@@ -1788,8 +1931,11 @@ unreg_dev:
+ free_dev:
+ kfree(dev);
+
+- v4l2_err(&dev->v4l2_dev,
+- "%s: error %d while loading driver\n",
++ for ( ; camera > 0; camera--) {
++ bcm2835_cleanup_instance(gdev[camera]);
++ gdev[camera] = NULL;
++ }
++ pr_info("%s: error %d while loading driver\n",
+ BM2835_MMAL_MODULE_NAME, ret);
+
+ return ret;
+@@ -1797,46 +1943,14 @@ free_dev:
+
+ static void __exit bm2835_mmal_exit(void)
+ {
+- if (!gdev)
+- return;
+-
+- v4l2_info(&gdev->v4l2_dev, "unregistering %s\n",
+- video_device_node_name(&gdev->vdev));
++ int camera;
++ struct vchiq_mmal_instance *instance = gdev[0]->instance;
+
+- video_unregister_device(&gdev->vdev);
+-
+- if (gdev->capture.encode_component) {
+- v4l2_dbg(1, bcm2835_v4l2_debug, &gdev->v4l2_dev,
+- "mmal_exit - disconnect tunnel\n");
+- vchiq_mmal_port_connect_tunnel(gdev->instance,
+- gdev->capture.camera_port, NULL);
+- vchiq_mmal_component_disable(gdev->instance,
+- gdev->capture.encode_component);
++ for (camera = 0; camera < MAX_BCM2835_CAMERAS; camera++) {
++ bcm2835_cleanup_instance(gdev[camera]);
++ gdev[camera] = NULL;
+ }
+- vchiq_mmal_component_disable(gdev->instance,
+- gdev->component[MMAL_COMPONENT_CAMERA]);
+-
+- vchiq_mmal_component_finalise(gdev->instance,
+- gdev->
+- component[MMAL_COMPONENT_VIDEO_ENCODE]);
+-
+- vchiq_mmal_component_finalise(gdev->instance,
+- gdev->
+- component[MMAL_COMPONENT_IMAGE_ENCODE]);
+-
+- vchiq_mmal_component_finalise(gdev->instance,
+- gdev->component[MMAL_COMPONENT_PREVIEW]);
+-
+- vchiq_mmal_component_finalise(gdev->instance,
+- gdev->component[MMAL_COMPONENT_CAMERA]);
+-
+- vchiq_mmal_finalise(gdev->instance);
+-
+- v4l2_ctrl_handler_free(&gdev->ctrl_handler);
+-
+- v4l2_device_unregister(&gdev->v4l2_dev);
+-
+- kfree(gdev);
++ vchiq_mmal_finalise(instance);
+ }
+
+ module_init(bm2835_mmal_init);
+--- a/drivers/media/platform/bcm2835/bcm2835-camera.h
++++ b/drivers/media/platform/bcm2835/bcm2835-camera.h
+@@ -15,7 +15,7 @@
+ * core driver device
+ */
+
+-#define V4L2_CTRL_COUNT 28 /* number of v4l controls */
++#define V4L2_CTRL_COUNT 29 /* number of v4l controls */
+
+ enum {
+ MMAL_COMPONENT_CAMERA = 0,
+@@ -58,6 +58,8 @@ struct bm2835_mmal_dev {
+ enum mmal_parameter_exposuremeteringmode metering_mode;
+ unsigned int manual_shutter_speed;
+ bool exp_auto_priority;
++ bool manual_iso_enabled;
++ uint32_t iso;
+
+ /* allocated mmal instance and components */
+ struct vchiq_mmal_instance *instance;
+@@ -104,6 +106,8 @@ struct bm2835_mmal_dev {
+
+ } capture;
+
++ unsigned int camera_num;
++
+ };
+
+ int bm2835_mmal_init_controls(
+@@ -124,3 +128,16 @@ int set_framerate_params(struct bm2835_m
+ (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \
+ (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \
+ }
++#define v4l2_dump_win_format(level, debug, dev, win_fmt, desc) \
++{ \
++ v4l2_dbg(level, debug, dev, \
++"%s: w %u h %u l %u t %u field %u chromakey %06X clip %p " \
++"clipcount %u bitmap %p\n", \
++ desc == NULL ? "" : desc, \
++ (win_fmt)->w.width, (win_fmt)->w.height, \
++ (win_fmt)->w.left, (win_fmt)->w.top, \
++ (win_fmt)->field, \
++ (win_fmt)->chromakey, \
++ (win_fmt)->clips, (win_fmt)->clipcount, \
++ (win_fmt)->bitmap); \
++}
+--- a/drivers/media/platform/bcm2835/controls.c
++++ b/drivers/media/platform/bcm2835/controls.c
+@@ -49,10 +49,13 @@ static const s64 ev_bias_qmenu[] = {
+ 4000
+ };
+
+-/* Supported ISO values
++/* Supported ISO values (*1000)
+ * ISOO = auto ISO
+ */
+ static const s64 iso_qmenu[] = {
++ 0, 100000, 200000, 400000, 800000,
++};
++static const uint32_t iso_values[] = {
+ 0, 100, 200, 400, 800,
+ };
+
+@@ -201,7 +204,7 @@ static int ctrl_set_value(struct bm2835_
+ &u32_value, sizeof(u32_value));
+ }
+
+-static int ctrl_set_value_menu(struct bm2835_mmal_dev *dev,
++static int ctrl_set_iso(struct bm2835_mmal_dev *dev,
+ struct v4l2_ctrl *ctrl,
+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl)
+ {
+@@ -211,12 +214,23 @@ static int ctrl_set_value_menu(struct bm
+ if (ctrl->val > mmal_ctrl->max || ctrl->val < mmal_ctrl->min)
+ return 1;
+
++ if (ctrl->id == V4L2_CID_ISO_SENSITIVITY)
++ dev->iso = iso_values[ctrl->val];
++ else if (ctrl->id == V4L2_CID_ISO_SENSITIVITY_AUTO)
++ dev->manual_iso_enabled =
++ (ctrl->val == V4L2_ISO_SENSITIVITY_MANUAL ?
++ true :
++ false);
++
+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control;
+
+- u32_value = mmal_ctrl->imenu[ctrl->val];
++ if (dev->manual_iso_enabled)
++ u32_value = dev->iso;
++ else
++ u32_value = 0;
+
+ return vchiq_mmal_port_parameter_set(dev->instance, control,
+- mmal_ctrl->mmal_id,
++ MMAL_PARAMETER_ISO,
+ &u32_value, sizeof(u32_value));
+ }
+
+@@ -956,7 +970,14 @@ static const struct bm2835_mmal_v4l2_ctr
+ V4L2_CID_ISO_SENSITIVITY, MMAL_CONTROL_TYPE_INT_MENU,
+ 0, ARRAY_SIZE(iso_qmenu) - 1, 0, 1, iso_qmenu,
+ MMAL_PARAMETER_ISO,
+- &ctrl_set_value_menu,
++ &ctrl_set_iso,
++ false
++ },
++ {
++ V4L2_CID_ISO_SENSITIVITY_AUTO, MMAL_CONTROL_TYPE_STD_MENU,
++ 0, 1, V4L2_ISO_SENSITIVITY_AUTO, 1, NULL,
++ MMAL_PARAMETER_ISO,
++ &ctrl_set_iso,
+ false
+ },
+ {
+--- a/drivers/media/platform/bcm2835/mmal-parameters.h
++++ b/drivers/media/platform/bcm2835/mmal-parameters.h
+@@ -654,3 +654,36 @@ struct mmal_parameter_imagefx_parameters
+ u32 num_effect_params;
+ u32 effect_parameter[MMAL_MAX_IMAGEFX_PARAMETERS];
+ };
++
++#define MMAL_PARAMETER_CAMERA_INFO_MAX_CAMERAS 4
++#define MMAL_PARAMETER_CAMERA_INFO_MAX_FLASHES 2
++#define MMAL_PARAMETER_CAMERA_INFO_MAX_STR_LEN 16
++
++struct mmal_parameter_camera_info_camera_t {
++ u32 port_id;
++ u32 max_width;
++ u32 max_height;
++ u32 lens_present;
++ u8 camera_name[MMAL_PARAMETER_CAMERA_INFO_MAX_STR_LEN];
++};
++
++enum mmal_parameter_camera_info_flash_type_t {
++ /* Make values explicit to ensure they match values in config ini */
++ MMAL_PARAMETER_CAMERA_INFO_FLASH_TYPE_XENON = 0,
++ MMAL_PARAMETER_CAMERA_INFO_FLASH_TYPE_LED = 1,
++ MMAL_PARAMETER_CAMERA_INFO_FLASH_TYPE_OTHER = 2,
++ MMAL_PARAMETER_CAMERA_INFO_FLASH_TYPE_MAX = 0x7FFFFFFF
++};
++
++struct mmal_parameter_camera_info_flash_t {
++ enum mmal_parameter_camera_info_flash_type_t flash_type;
++};
++
++struct mmal_parameter_camera_info_t {
++ u32 num_cameras;
++ u32 num_flashes;
++ struct mmal_parameter_camera_info_camera_t
++ cameras[MMAL_PARAMETER_CAMERA_INFO_MAX_CAMERAS];
++ struct mmal_parameter_camera_info_flash_t
++ flashes[MMAL_PARAMETER_CAMERA_INFO_MAX_FLASHES];
++};
--- /dev/null
+From 6a5e76800cf6d16d01b8e186806decc047590e46 Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Mon, 11 Apr 2016 12:50:58 +0100
+Subject: [PATCH 234/304] bcm2835-sdhost: Reset the clock in task context
+
+Since reprogramming the clock can now involve a round-trip to the
+firmware it must not be done at atomic context, and a tasklet
+is not a task.
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ drivers/mmc/host/bcm2835-sdhost.c | 25 ++++++++++++++++++-------
+ 1 file changed, 18 insertions(+), 7 deletions(-)
+
+--- a/drivers/mmc/host/bcm2835-sdhost.c
++++ b/drivers/mmc/host/bcm2835-sdhost.c
+@@ -185,6 +185,7 @@ struct bcm2835_host {
+
+ unsigned int debug:1; /* Enable debug output */
+ unsigned int firmware_sets_cdiv:1; /* Let the firmware manage the clock */
++ unsigned int reset_clock:1; /* Reset the clock fore the next request */
+
+ /*DMA part*/
+ struct dma_chan *dma_chan_rxtx; /* DMA channel for reads and writes */
+@@ -1505,6 +1506,7 @@ void bcm2835_sdhost_set_clock(struct bcm
+ {
+ int div = 0; /* Initialized for compiler warning */
+ unsigned int input_clock = clock;
++ unsigned long flags;
+
+ if (host->debug)
+ pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock);
+@@ -1544,13 +1546,17 @@ void bcm2835_sdhost_set_clock(struct bcm
+ &msg, sizeof(msg));
+
+ clock = max(msg[1], msg[2]);
++ spin_lock_irqsave(&host->lock, flags);
+ } else {
++ spin_lock_irqsave(&host->lock, flags);
+ if (clock < 100000) {
+ /* Can't stop the clock, but make it as slow as
+ * possible to show willing
+ */
+ host->cdiv = SDCDIV_MAX_CDIV;
+ bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
++ mmiowb();
++ spin_unlock_irqrestore(&host->lock, flags);
+ return;
+ }
+
+@@ -1605,6 +1611,11 @@ void bcm2835_sdhost_set_clock(struct bcm
+ bcm2835_sdhost_write(host, clock/2, SDTOUT);
+
+ host->mmc->actual_clock = clock;
++ host->clock = input_clock;
++ host->reset_clock = 0;
++
++ mmiowb();
++ spin_unlock_irqrestore(&host->lock, flags);
+ }
+
+ static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq)
+@@ -1653,6 +1664,9 @@ static void bcm2835_sdhost_request(struc
+ (mrq->data->blocks > host->pio_limit))
+ bcm2835_sdhost_prepare_dma(host, mrq->data);
+
++ if (host->reset_clock)
++ bcm2835_sdhost_set_clock(host, host->clock);
++
+ spin_lock_irqsave(&host->lock, flags);
+
+ WARN_ON(host->mrq != NULL);
+@@ -1731,14 +1745,12 @@ static void bcm2835_sdhost_set_ios(struc
+
+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
+
+- if (!ios->clock || ios->clock != host->clock) {
+- bcm2835_sdhost_set_clock(host, ios->clock);
+- host->clock = ios->clock;
+- }
+-
+ mmiowb();
+
+ spin_unlock_irqrestore(&host->lock, flags);
++
++ if (!ios->clock || ios->clock != host->clock)
++ bcm2835_sdhost_set_clock(host, ios->clock);
+ }
+
+ static struct mmc_host_ops bcm2835_sdhost_ops = {
+@@ -1810,7 +1822,7 @@ static void bcm2835_sdhost_tasklet_finis
+ host->overclock_50--;
+ pr_warn("%s: reducing overclock due to errors\n",
+ mmc_hostname(host->mmc));
+- bcm2835_sdhost_set_clock(host,50*MHZ);
++ host->reset_clock = 1;
+ mrq->cmd->error = -EILSEQ;
+ mrq->cmd->retries = 1;
+ }
+@@ -1979,7 +1991,6 @@ static int bcm2835_sdhost_probe(struct p
+ mmc->ops = &bcm2835_sdhost_ops;
+ host = mmc_priv(mmc);
+ host->mmc = mmc;
+- host->cmd_quick_poll_retries = 0;
+ host->pio_timeout = msecs_to_jiffies(500);
+ host->pio_limit = 1;
+ host->max_delay = 1; /* Warn if over 1ms */
--- /dev/null
+From c4297390ed5ba3e78012fdc4d688710dc610dfe6 Mon Sep 17 00:00:00 2001
+From: popcornmix <popcornmix@gmail.com>
+Date: Thu, 7 Apr 2016 12:44:24 +0100
+Subject: [PATCH 235/304] config: Enable CONFIG_IPV6_ROUTER_PREF for networks
+ with multiple routers
+
+---
+ arch/arm/configs/bcm2709_defconfig | 1 +
+ arch/arm/configs/bcmrpi_defconfig | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/arch/arm/configs/bcm2709_defconfig
++++ b/arch/arm/configs/bcm2709_defconfig
+@@ -101,6 +101,7 @@ CONFIG_INET_XFRM_MODE_TUNNEL=m
+ CONFIG_INET_XFRM_MODE_BEET=m
+ CONFIG_INET_LRO=m
+ CONFIG_INET_DIAG=m
++CONFIG_IPV6_ROUTER_PREF=y
+ CONFIG_INET6_AH=m
+ CONFIG_INET6_ESP=m
+ CONFIG_INET6_IPCOMP=m
+--- a/arch/arm/configs/bcmrpi_defconfig
++++ b/arch/arm/configs/bcmrpi_defconfig
+@@ -95,6 +95,7 @@ CONFIG_INET_XFRM_MODE_TUNNEL=m
+ CONFIG_INET_XFRM_MODE_BEET=m
+ CONFIG_INET_LRO=m
+ CONFIG_INET_DIAG=m
++CONFIG_IPV6_ROUTER_PREF=y
+ CONFIG_INET6_AH=m
+ CONFIG_INET6_ESP=m
+ CONFIG_INET6_IPCOMP=m
--- /dev/null
+From 4ccd590e7579d86778b73d381dfe9082e5df7518 Mon Sep 17 00:00:00 2001
+From: jochenberger <fooberger@gmail.com>
+Date: Thu, 7 Apr 2016 21:38:46 +0200
+Subject: [PATCH 236/304] Enable hid-betopff module
+
+Add force feedback support for Betop based devices
+https://github.com/raspberrypi/linux/blob/rpi-4.1.y/drivers/hid/hid-betopff.c
+---
+ arch/arm/configs/bcm2709_defconfig | 1 +
+ arch/arm/configs/bcmrpi_defconfig | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/arch/arm/configs/bcm2709_defconfig
++++ b/arch/arm/configs/bcm2709_defconfig
+@@ -867,6 +867,7 @@ CONFIG_HID_A4TECH=m
+ CONFIG_HID_ACRUX=m
+ CONFIG_HID_APPLE=m
+ CONFIG_HID_BELKIN=m
++CONFIG_HID_BETOP_FF=m
+ CONFIG_HID_CHERRY=m
+ CONFIG_HID_CHICONY=m
+ CONFIG_HID_CYPRESS=m
+--- a/arch/arm/configs/bcmrpi_defconfig
++++ b/arch/arm/configs/bcmrpi_defconfig
+@@ -859,6 +859,7 @@ CONFIG_HID_A4TECH=m
+ CONFIG_HID_ACRUX=m
+ CONFIG_HID_APPLE=m
+ CONFIG_HID_BELKIN=m
++CONFIG_HID_BETOP_FF=m
+ CONFIG_HID_CHERRY=m
+ CONFIG_HID_CHICONY=m
+ CONFIG_HID_CYPRESS=m
--- /dev/null
+From bf0e127060951623a842c078b18585afff833227 Mon Sep 17 00:00:00 2001
+From: popcornmix <popcornmix@gmail.com>
+Date: Tue, 12 Apr 2016 12:45:16 +0100
+Subject: [PATCH 237/304] config: Make IPV6 a module and regenerate with
+ defconfig
+
+---
+ arch/arm/configs/bcm2709_defconfig | 4 ++--
+ arch/arm/configs/bcmrpi_defconfig | 6 +++---
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/arm/configs/bcm2709_defconfig
++++ b/arch/arm/configs/bcm2709_defconfig
+@@ -101,6 +101,7 @@ CONFIG_INET_XFRM_MODE_TUNNEL=m
+ CONFIG_INET_XFRM_MODE_BEET=m
+ CONFIG_INET_LRO=m
+ CONFIG_INET_DIAG=m
++CONFIG_IPV6=m
+ CONFIG_IPV6_ROUTER_PREF=y
+ CONFIG_INET6_AH=m
+ CONFIG_INET6_ESP=m
+@@ -600,10 +601,9 @@ CONFIG_HW_RANDOM=y
+ CONFIG_RAW_DRIVER=y
+ CONFIG_I2C=y
+ CONFIG_I2C_CHARDEV=m
++CONFIG_I2C_MUX_PCA954x=m
+ CONFIG_I2C_BCM2708=m
+ CONFIG_I2C_GPIO=m
+-CONFIG_I2C_MUX=m
+-CONFIG_I2C_MUX_PCA954x=m
+ CONFIG_SPI=y
+ CONFIG_SPI_BCM2835=m
+ CONFIG_SPI_BCM2835AUX=m
+--- a/arch/arm/configs/bcmrpi_defconfig
++++ b/arch/arm/configs/bcmrpi_defconfig
+@@ -73,7 +73,6 @@ CONFIG_INET=y
+ CONFIG_IP_MULTICAST=y
+ CONFIG_IP_ADVANCED_ROUTER=y
+ CONFIG_IP_MULTIPLE_TABLES=y
+-CONFIG_IPV6_SUBTREES=y
+ CONFIG_IP_ROUTE_MULTIPATH=y
+ CONFIG_IP_ROUTE_VERBOSE=y
+ CONFIG_IP_PNP=y
+@@ -95,12 +94,14 @@ CONFIG_INET_XFRM_MODE_TUNNEL=m
+ CONFIG_INET_XFRM_MODE_BEET=m
+ CONFIG_INET_LRO=m
+ CONFIG_INET_DIAG=m
++CONFIG_IPV6=m
+ CONFIG_IPV6_ROUTER_PREF=y
+ CONFIG_INET6_AH=m
+ CONFIG_INET6_ESP=m
+ CONFIG_INET6_IPCOMP=m
+ CONFIG_IPV6_TUNNEL=m
+ CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_SUBTREES=y
+ CONFIG_IPV6_MROUTE=y
+ CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+ CONFIG_IPV6_PIMSM_V2=y
+@@ -593,10 +594,9 @@ CONFIG_HW_RANDOM=y
+ CONFIG_RAW_DRIVER=y
+ CONFIG_I2C=y
+ CONFIG_I2C_CHARDEV=m
++CONFIG_I2C_MUX_PCA954x=m
+ CONFIG_I2C_BCM2708=m
+ CONFIG_I2C_GPIO=m
+-CONFIG_I2C_MUX=m
+-CONFIG_I2C_MUX_PCA954x=m
+ CONFIG_SPI=y
+ CONFIG_SPI_BCM2835=m
+ CONFIG_SPI_BCM2835AUX=m
--- /dev/null
+From 3533e797aaf506f1e81a3b53bf04ce9592005756 Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Tue, 5 Apr 2016 13:01:54 +0100
+Subject: [PATCH 238/304] BCM270X_DT: Add dpi24 overlay
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ arch/arm/boot/dts/overlays/Makefile | 1 +
+ arch/arm/boot/dts/overlays/README | 8 +++++++
+ arch/arm/boot/dts/overlays/dpi24-overlay.dts | 31 ++++++++++++++++++++++++++++
+ 3 files changed, 40 insertions(+)
+ create mode 100644 arch/arm/boot/dts/overlays/dpi24-overlay.dts
+
+--- a/arch/arm/boot/dts/overlays/Makefile
++++ b/arch/arm/boot/dts/overlays/Makefile
+@@ -15,6 +15,7 @@ endif
+ dtbo-$(RPI_DT_OVERLAYS) += ads7846.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += at86rf233.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor.dtbo
++dtbo-$(RPI_DT_OVERLAYS) += dpi24.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += dwc2.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += dwc-otg.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += dht11.dtbo
+--- a/arch/arm/boot/dts/overlays/README
++++ b/arch/arm/boot/dts/overlays/README
+@@ -213,6 +213,14 @@ Params: gpiopin GPIO con
+ (default 4)
+
+
++Name: dpi24
++Info: Overlay for a generic 24-bit DPI display
++ This uses GPIOs 0-27 (so no I2C, uart etc.), and activates the output
++ 2-3 seconds after the kernel has started.
++Load: dtoverlay=dpi24
++Params: <None>
++
++
+ Name: dwc-otg
+ Info: Selects the dwc_otg USB controller driver which has fiq support. This
+ is the default on all except the Pi Zero which defaults to dwc2.
+--- /dev/null
++++ b/arch/arm/boot/dts/overlays/dpi24-overlay.dts
+@@ -0,0 +1,31 @@
++/dts-v1/;
++/plugin/;
++
++/{
++ compatible = "brcm,bcm2708";
++
++ // There is no DPI driver module, but we need a platform device
++ // node (that doesn't already use pinctrl) to hang the pinctrl
++ // reference on - leds will do
++
++ fragment@0 {
++ target = <&leds>;
++ __overlay__ {
++ pinctrl-names = "default";
++ pinctrl-0 = <&dpi24_pins>;
++ };
++ };
++
++ fragment@1 {
++ target = <&gpio>;
++ __overlay__ {
++ dpi24_pins: dpi24_pins {
++ brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
++ 12 13 14 15 16 17 18 19 20
++ 21 22 23 24 25 26 27>;
++ brcm,function = <6>; /* alt2 */
++ brcm,pull = <0>; /* no pull */
++ };
++ };
++ };
++};
--- /dev/null
+From 9f531cf57594be3a2d0eb4502c301ceadcc612cd Mon Sep 17 00:00:00 2001
+From: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
+Date: Thu, 14 Apr 2016 00:57:33 +0100
+Subject: [PATCH 239/304] Modify IQAudIO DAC+ ASoC driver to set card/dai
+ config from dt
+
+Add the ability to set the card name, dai name and dai stream name, from
+dt config.
+
+Signed-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
+---
+ sound/soc/bcm/iqaudio-dac.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+--- a/sound/soc/bcm/iqaudio-dac.c
++++ b/sound/soc/bcm/iqaudio-dac.c
+@@ -61,8 +61,6 @@ static struct snd_soc_ops snd_rpi_iqaudi
+
+ static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = {
+ {
+- .name = "IQaudIO DAC",
+- .stream_name = "IQaudIO DAC HiFi",
+ .cpu_dai_name = "bcm2708-i2s.0",
+ .codec_dai_name = "pcm512x-hifi",
+ .platform_name = "bcm2708-i2s.0",
+@@ -76,7 +74,6 @@ static struct snd_soc_dai_link snd_rpi_i
+
+ /* audio machine driver */
+ static struct snd_soc_card snd_rpi_iqaudio_dac = {
+- .name = "IQaudIODAC",
+ .owner = THIS_MODULE,
+ .dai_link = snd_rpi_iqaudio_dac_dai,
+ .num_links = ARRAY_SIZE(snd_rpi_iqaudio_dac_dai),
+@@ -90,6 +87,7 @@ static int snd_rpi_iqaudio_dac_probe(str
+
+ if (pdev->dev.of_node) {
+ struct device_node *i2s_node;
++ struct snd_soc_card *card = &snd_rpi_iqaudio_dac;
+ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0];
+ i2s_node = of_parse_phandle(pdev->dev.of_node,
+ "i2s-controller", 0);
+@@ -103,6 +101,15 @@ static int snd_rpi_iqaudio_dac_probe(str
+
+ digital_gain_0db_limit = !of_property_read_bool(pdev->dev.of_node,
+ "iqaudio,24db_digital_gain");
++ if (of_property_read_string(pdev->dev.of_node, "card_name",
++ &card->name))
++ card->name = "IQaudIODAC";
++ if (of_property_read_string(pdev->dev.of_node, "dai_name",
++ &dai->name))
++ dai->name = "IQaudIO DAC";
++ if (of_property_read_string(pdev->dev.of_node, "dai_stream_name",
++ &dai->stream_name))
++ dai->stream_name = "IQaudIO DAC HiFi";
+ }
+
+ ret = snd_soc_register_card(&snd_rpi_iqaudio_dac);
--- /dev/null
+From ddef7a853652982c2796db7f43d067d8487bc7e9 Mon Sep 17 00:00:00 2001
+From: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
+Date: Thu, 14 Apr 2016 01:00:58 +0100
+Subject: [PATCH 240/304] Add support for the Digital Dreamtime Akkordion music
+ player.
+
+Support the Digital Dreamtime Akkordion using the OEM IQAudIO DAC+ or
+DACZero modules. Set ALSA card name, ("Akkordion"), from dt config.
+
+Signed-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>
+---
+ arch/arm/boot/dts/overlays/Makefile | 1 +
+ arch/arm/boot/dts/overlays/README | 20 ++++++++++
+ .../dts/overlays/akkordion-iqdacplus-overlay.dts | 46 ++++++++++++++++++++++
+ 3 files changed, 67 insertions(+)
+ create mode 100644 arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts
+
+--- a/arch/arm/boot/dts/overlays/Makefile
++++ b/arch/arm/boot/dts/overlays/Makefile
+@@ -13,6 +13,7 @@ ifeq ($(CONFIG_ARCH_BCM2835),y)
+ endif
+
+ dtbo-$(RPI_DT_OVERLAYS) += ads7846.dtbo
++dtbo-$(RPI_DT_OVERLAYS) += akkordion-iqdacplus.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += at86rf233.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += dpi24.dtbo
+--- a/arch/arm/boot/dts/overlays/README
++++ b/arch/arm/boot/dts/overlays/README
+@@ -186,6 +186,26 @@ Params: cs SPI bus
+ www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt
+
+
++Name: akkordion-iqdacplus
++Info: Configures the Digital Dreamtime Akkordion Music Player (based on the
++ OEM IQAudIO DAC+ or DAC Zero module).
++Load: dtoverlay=akkordion-iqdacplus,<param>=<val>
++Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec
++ Digital volume control. Enable with
++ dtoverlay=akkordion-iqdacplus,24db_digital_gain
++ (The default behaviour is that the Digital
++ volume control is limited to a maximum of
++ 0dB. ie. it can attenuate but not provide
++ gain. For most users, this will be desired
++ as it will prevent clipping. By appending
++ the 24db_digital_gain parameter, the Digital
++ volume control will allow up to 24dB of
++ gain. If this parameter is enabled, it is the
++ responsibility of the user to ensure that
++ the Digital volume control is set to a value
++ that does not result in clipping/distortion!)
++
++
+ Name: at86rf233
+ Info: Configures the Atmel AT86RF233 802.15.4 low-power WPAN transceiver,
+ connected to spi0.0
+--- /dev/null
++++ b/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts
+@@ -0,0 +1,46 @@
++// Definitions for Digital Dreamtime Akkordion using IQaudIO DAC+ or DACZero
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ frag0: __overlay__ {
++ compatible = "iqaudio,iqaudio-dac";
++ card_name = "Akkordion";
++ dai_name = "IQaudIO DAC";
++ dai_stream_name = "IQaudIO DAC HiFi";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ pcm5122@4c {
++ #sound-dai-cells = <0>;
++ compatible = "ti,pcm5122";
++ reg = <0x4c>;
++ status = "okay";
++ };
++ };
++ };
++
++ __overrides__ {
++ 24db_digital_gain = <&frag0>,"iqaudio,24db_digital_gain?";
++ };
++};
--- /dev/null
+From e064c9d7ec3c51b79c6fdb7f1ff3a07b246ea774 Mon Sep 17 00:00:00 2001
+From: Aaron Shaw <shawaj@gmail.com>
+Date: Thu, 7 Apr 2016 21:26:21 +0100
+Subject: [PATCH 241/304] Add Support for BoomBerry Audio boards
+
+---
+ arch/arm/boot/dts/overlays/Makefile | 2 +
+ arch/arm/boot/dts/overlays/README | 26 +++
+ .../boot/dts/overlays/boomberry-dac-overlay.dts | 43 +++++
+ .../boot/dts/overlays/boomberry-digi-overlay.dts | 39 ++++
+ arch/arm/configs/bcm2709_defconfig | 2 +
+ arch/arm/configs/bcmrpi_defconfig | 2 +
+ sound/soc/bcm/Kconfig | 14 ++
+ sound/soc/bcm/Makefile | 4 +
+ sound/soc/bcm/boomberry-dac.c | 163 ++++++++++++++++
+ sound/soc/bcm/boomberry-digi.c | 215 +++++++++++++++++++++
+ 10 files changed, 510 insertions(+)
+ create mode 100644 arch/arm/boot/dts/overlays/boomberry-dac-overlay.dts
+ create mode 100644 arch/arm/boot/dts/overlays/boomberry-digi-overlay.dts
+ create mode 100644 sound/soc/bcm/boomberry-dac.c
+ create mode 100644 sound/soc/bcm/boomberry-digi.c
+
+--- a/arch/arm/boot/dts/overlays/Makefile
++++ b/arch/arm/boot/dts/overlays/Makefile
+@@ -16,6 +16,8 @@ dtbo-$(RPI_DT_OVERLAYS) += ads7846.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += akkordion-iqdacplus.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += at86rf233.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor.dtbo
++dtbo-$(RPI_DT_OVERLAYS) += boomberry-dac.dtbo
++dtbo-$(RPI_DT_OVERLAYS) += boomberry-digi.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += dpi24.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += dwc2.dtbo
+ dtbo-$(RPI_DT_OVERLAYS) += dwc-otg.dtbo
+--- a/arch/arm/boot/dts/overlays/README
++++ b/arch/arm/boot/dts/overlays/README
+@@ -225,6 +225,32 @@ Load: dtoverlay=bmp085_i2c-sensor
+ Params: <None>
+
+
++Name: boomberry-dac
++Info: Configures the BoomBerry DAC HAT, Amp HAT, DAC Zero and Amp Zero audio
++ cards
++Load: dtoverlay=boomberry-dac,<param>=<val>
++Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec
++ Digital volume control. Enable with
++ "dtoverlay=boomberry-dac,24db_digital_gain"
++ (The default behaviour is that the Digital
++ volume control is limited to a maximum of
++ 0dB. ie. it can attenuate but not provide
++ gain. For most users, this will be desired
++ as it will prevent clipping. By appending
++ the 24dB_digital_gain parameter, the Digital
++ volume control will allow up to 24dB of
++ gain. If this parameter is enabled, it is the
++ responsibility of the user to ensure that
++ the Digital volume control is set to a value
++ that does not result in clipping/distortion!)
++
++
++Name: boomberry-digi
++Info: Configures the BoomBerry Digi HAT and Digi Zero audio cards
++Load: dtoverlay=boomberry-digi
++Params: <None>
++
++
+ Name: dht11
+ Info: Overlay for the DHT11/DHT21/DHT22 humidity/temperature sensors
+ Also sometimes found with the part number(s) AM230x.
+--- /dev/null
++++ b/arch/arm/boot/dts/overlays/boomberry-dac-overlay.dts
+@@ -0,0 +1,43 @@
++// Definitions for BoomBerry DAC
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ frag0: __overlay__ {
++ compatible = "boomberry,boomberry-dac";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ pcm5122@4d {
++ #sound-dai-cells = <0>;
++ compatible = "ti,pcm5122";
++ reg = <0x4d>;
++ status = "okay";
++ };
++ };
++ };
++
++ __overrides__ {
++ 24db_digital_gain = <&frag0>,"boomberry,24db_digital_gain?";
++ };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/overlays/boomberry-digi-overlay.dts
+@@ -0,0 +1,39 @@
++// Definitions for BoomBerry Digi
++/dts-v1/;
++/plugin/;
++
++/ {
++ compatible = "brcm,bcm2708";
++
++ fragment@0 {
++ target = <&sound>;
++ __overlay__ {
++ compatible = "boomberry,boomberry-digi";
++ i2s-controller = <&i2s>;
++ status = "okay";
++ };
++ };
++
++ fragment@1 {
++ target = <&i2s>;
++ __overlay__ {
++ status = "okay";
++ };
++ };
++
++ fragment@2 {
++ target = <&i2c1>;
++ __overlay__ {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ wm8804@3b {
++ #sound-dai-cells = <0>;
++ compatible = "wlf,wm8804";
++ reg = <0x3b>;
++ status = "okay";
++ };
++ };
++ };
++};
+--- a/arch/arm/configs/bcm2709_defconfig
++++ b/arch/arm/configs/bcm2709_defconfig
+@@ -853,6 +853,8 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
++CONFIG_SND_BCM2708_SOC_BOOMBERRY_DAC=m
++CONFIG_SNG_BCM2708_SOC_BOOMBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_RPI_DAC=m
+ CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
+ CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
+--- a/arch/arm/configs/bcmrpi_defconfig
++++ b/arch/arm/configs/bcmrpi_defconfig
+@@ -845,6 +845,8 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
++CONFIG_SND_BCM2708_SOC_BOOMBERRY_DAC=m
++CONFIG_SND_BCM2708_SOC_BOOMBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_RPI_DAC=m
+ CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
+ CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
+--- a/sound/soc/bcm/Kconfig
++++ b/sound/soc/bcm/Kconfig
+@@ -50,6 +50,20 @@ config SND_BCM2708_SOC_RPI_PROTO
+ help
+ Say Y or M if you want to add support for Audio Codec Board PROTO (WM8731).
+
++config SND_BCM2708_SOC_BOOMBERRY_DAC
++ tristate "Support for BoomBerry DAC"
++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
++ select SND_SOC_PCM512x
++ help
++ Say Y or M if you want to add support for BoomBerry DAC.
++
++config SND_BCM2708_SOC_BOOMBERRY_DIGI
++ tristate "Support for BoomBerry Digi"
++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
++ select SND_SOC_WM8804
++ help
++ Say Y or M if you want to add support for BoomBerry Digi.
++
+ config SND_BCM2708_SOC_IQAUDIO_DAC
+ tristate "Support for IQaudIO-DAC"
+ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S
+--- a/sound/soc/bcm/Makefile
++++ b/sound/soc/bcm/Makefile
+@@ -8,6 +8,8 @@ snd-soc-hifiberry-dac-objs := hifiberry_
+ snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o
+ snd-soc-hifiberry-digi-objs := hifiberry_digi.o
+ snd-soc-hifiberry-amp-objs := hifiberry_amp.o
++snd-soc-boomberry-dac-objs := boomberry-dac.o
++snd-soc-boomberry-digi-objs := boomberry-digi.o
+ snd-soc-rpi-dac-objs := rpi-dac.o
+ snd-soc-rpi-proto-objs := rpi-proto.o
+ snd-soc-iqaudio-dac-objs := iqaudio-dac.o
+@@ -17,6 +19,8 @@ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_D
+ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o
+ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o
+ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o
++obj-$(CONFIG_SND_BCM2708_SOC_BOOMBERRY_DAC) += snd-soc-boomberry-dac.o
++obj-$(CONFIG_SND_BCM2708_SOC_BOOMBERRY_DIGI) += snd-soc-boomberry-digi.o
+ obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o
+ obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o
+ obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o
+--- /dev/null
++++ b/sound/soc/bcm/boomberry-dac.c
+@@ -0,0 +1,163 @@
++/*
++ * ASoC Driver for BoomBerry DAC Raspberry Pi HAT Sound Card
++ *
++ * Author: Milan Neskovic
++ * Copyright 2016
++ * based on code by Daniel Matuschek <info@crazy-audio.com>
++ * based on code by Florian Meier <florian.meier@koalo.de>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++
++#include "../codecs/pcm512x.h"
++
++static bool digital_gain_0db_limit = true;
++
++static int snd_rpi_boomberry_dac_init(struct snd_soc_pcm_runtime *rtd)
++{
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08);
++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02);
++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
++
++ if (digital_gain_0db_limit)
++ {
++ int ret;
++ struct snd_soc_card *card = rtd->card;
++ struct snd_soc_codec *codec = rtd->codec;
++
++ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207);
++ if (ret < 0)
++ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
++ }
++
++ return 0;
++}
++
++static int snd_rpi_boomberry_dac_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ /*return snd_soc_dai_set_bclk_ratio(cpu_dai, 64);*/
++ unsigned int sample_bits =
++ snd_pcm_format_physical_width(params_format(params));
++ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);
++}
++
++static int snd_rpi_boomberry_dac_startup(struct snd_pcm_substream *substream) {
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08);
++ return 0;
++}
++
++static void snd_rpi_boomberry_dac_shutdown(struct snd_pcm_substream *substream) {
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00);
++}
++
++/* machine stream operations */
++static struct snd_soc_ops snd_rpi_boomberry_dac_ops = {
++ .hw_params = snd_rpi_boomberry_dac_hw_params,
++ .startup = snd_rpi_boomberry_dac_startup,
++ .shutdown = snd_rpi_boomberry_dac_shutdown,
++};
++
++static struct snd_soc_dai_link snd_rpi_boomberry_dac_dai[] = {
++{
++ .name = "BoomBerry DAC",
++ .stream_name = "BoomBerry DAC HiFi",
++ .cpu_dai_name = "bcm2708-i2s.0",
++ .codec_dai_name = "pcm512x-hifi",
++ .platform_name = "bcm2708-i2s.0",
++ .codec_name = "pcm512x.1-004d",
++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS,
++ .ops = &snd_rpi_boomberry_dac_ops,
++ .init = snd_rpi_boomberry_dac_init,
++},
++};
++
++/* audio machine driver */
++static struct snd_soc_card snd_rpi_boomberry_dac = {
++ .name = "snd_rpi_boomberry_dac",
++ .owner = THIS_MODULE,
++ .dai_link = snd_rpi_boomberry_dac_dai,
++ .num_links = ARRAY_SIZE(snd_rpi_boomberry_dac_dai),
++};
++
++static int snd_rpi_boomberry_dac_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ snd_rpi_boomberry_dac.dev = &pdev->dev;
++
++ if (pdev->dev.of_node) {
++ struct device_node *i2s_node;
++ struct snd_soc_dai_link *dai = &snd_rpi_boomberry_dac_dai[0];
++ i2s_node = of_parse_phandle(pdev->dev.of_node,
++ "i2s-controller", 0);
++
++ if (i2s_node) {
++ dai->cpu_dai_name = NULL;
++ dai->cpu_of_node = i2s_node;
++ dai->platform_name = NULL;
++ dai->platform_of_node = i2s_node;
++ }
++
++ digital_gain_0db_limit = !of_property_read_bool(
++ pdev->dev.of_node, "boomberry,24db_digital_gain");
++ }
++
++ ret = snd_soc_register_card(&snd_rpi_boomberry_dac);
++ if (ret)
++ dev_err(&pdev->dev,
++ "snd_soc_register_card() failed: %d\n", ret);
++
++ return ret;
++}
++
++static int snd_rpi_boomberry_dac_remove(struct platform_device *pdev)
++{
++ return snd_soc_unregister_card(&snd_rpi_boomberry_dac);
++}
++
++static const struct of_device_id snd_rpi_boomberry_dac_of_match[] = {
++ { .compatible = "boomberry,boomberry-dac", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snd_rpi_boomberry_dac_of_match);
++
++static struct platform_driver snd_rpi_boomberry_dac_driver = {
++ .driver = {
++ .name = "snd-rpi-boomberry-dac",
++ .owner = THIS_MODULE,
++ .of_match_table = snd_rpi_boomberry_dac_of_match,
++ },
++ .probe = snd_rpi_boomberry_dac_probe,
++ .remove = snd_rpi_boomberry_dac_remove,
++};
++
++module_platform_driver(snd_rpi_boomberry_dac_driver);
++
++MODULE_AUTHOR("Milan Neskovic <info@boomberry.co>");
++MODULE_DESCRIPTION("ASoC Driver for BoomBerry PI DAC HAT Sound Card");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/sound/soc/bcm/boomberry-digi.c
+@@ -0,0 +1,215 @@
++/*
++ * ASoC Driver for BoomBerry Raspberry Pi Digi HAT Sound Card
++ *
++ * Author: Milan Neskovic
++ * Copyright 2016
++ * based on code by Daniel Matuschek <info@crazy-audio.com>
++ * based on code by Florian Meier <florian.meier@koalo.de>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++
++#include "../codecs/wm8804.h"
++
++static int snd_rpi_boomberry_digi_init(struct snd_soc_pcm_runtime *rtd)
++{
++ struct snd_soc_codec *codec = rtd->codec;
++
++ /* enable TX output */
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
++
++ return 0;
++}
++
++static int snd_rpi_boomberry_digi_startup(struct snd_pcm_substream *substream) {
++ /* turn on digital output */
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00);
++ return 0;
++}
++
++static void snd_rpi_boomberry_digi_shutdown(struct snd_pcm_substream *substream) {
++ /* turn off output */
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c);
++}
++
++static int snd_rpi_boomberry_digi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct snd_soc_codec *codec = rtd->codec;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++
++ int sysclk = 27000000; /* This is fixed on this board */
++
++ long mclk_freq=0;
++ int mclk_div=1;
++ int sampling_freq=1;
++
++ int ret;
++
++ int samplerate = params_rate(params);
++
++ if (samplerate<=96000) {
++ mclk_freq=samplerate*256;
++ mclk_div=WM8804_MCLKDIV_256FS;
++ } else {
++ mclk_freq=samplerate*128;
++ mclk_div=WM8804_MCLKDIV_128FS;
++ }
++
++ switch (samplerate) {
++ case 32000:
++ sampling_freq=0x03;
++ break;
++ case 44100:
++ sampling_freq=0x00;
++ break;
++ case 48000:
++ sampling_freq=0x02;
++ break;
++ case 88200:
++ sampling_freq=0x08;
++ break;
++ case 96000:
++ sampling_freq=0x0a;
++ break;
++ case 176400:
++ sampling_freq=0x0c;
++ break;
++ case 192000:
++ sampling_freq=0x0e;
++ break;
++ default:
++ dev_err(codec->dev,
++ "Failed to set WM8804 SYSCLK, unsupported samplerate %d\n",
++ samplerate);
++ }
++
++ snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);
++ snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);
++
++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,
++ sysclk, SND_SOC_CLOCK_OUT);
++ if (ret < 0) {
++ dev_err(codec->dev,
++ "Failed to set WM8804 SYSCLK: %d\n", ret);
++ return ret;
++ }
++
++ /* Enable TX output */
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0);
++
++ /* Power on */
++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
++
++ /* set sampling frequency status bits */
++ snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq);
++
++ return snd_soc_dai_set_bclk_ratio(cpu_dai,64);
++}
++
++/* machine stream operations */
++static struct snd_soc_ops snd_rpi_boomberry_digi_ops = {
++ .hw_params = snd_rpi_boomberry_digi_hw_params,
++ .startup = snd_rpi_boomberry_digi_startup,
++ .shutdown = snd_rpi_boomberry_digi_shutdown,
++};
++
++static struct snd_soc_dai_link snd_rpi_boomberry_digi_dai[] = {
++{
++ .name = "BoomBerry Digi",
++ .stream_name = "BoomBerry Digi HiFi",
++ .cpu_dai_name = "bcm2708-i2s.0",
++ .codec_dai_name = "wm8804-spdif",
++ .platform_name = "bcm2708-i2s.0",
++ .codec_name = "wm8804.1-003b",
++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM,
++ .ops = &snd_rpi_boomberry_digi_ops,
++ .init = snd_rpi_boomberry_digi_init,
++},
++};
++
++/* audio machine driver */
++static struct snd_soc_card snd_rpi_boomberry_digi = {
++ .name = "snd_rpi_boomberry_digi",
++ .owner = THIS_MODULE,
++ .dai_link = snd_rpi_boomberry_digi_dai,
++ .num_links = ARRAY_SIZE(snd_rpi_boomberry_digi_dai),
++};
++
++static int snd_rpi_boomberry_digi_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ snd_rpi_boomberry_digi.dev = &pdev->dev;
++
++ if (pdev->dev.of_node) {
++ struct device_node *i2s_node;
++ struct snd_soc_dai_link *dai = &snd_rpi_boomberry_digi_dai[0];
++ i2s_node = of_parse_phandle(pdev->dev.of_node,
++ "i2s-controller", 0);
++
++ if (i2s_node) {
++ dai->cpu_dai_name = NULL;
++ dai->cpu_of_node = i2s_node;
++ dai->platform_name = NULL;
++ dai->platform_of_node = i2s_node;
++ }
++ }
++
++ ret = snd_soc_register_card(&snd_rpi_boomberry_digi);
++ if (ret)
++ dev_err(&pdev->dev,
++ "snd_soc_register_card() failed: %d\n", ret);
++
++ return ret;
++}
++
++static int snd_rpi_boomberry_digi_remove(struct platform_device *pdev)
++{
++ return snd_soc_unregister_card(&snd_rpi_boomberry_digi);
++}
++
++static const struct of_device_id snd_rpi_boomberry_digi_of_match[] = {
++ { .compatible = "boomberry,boomberry-digi", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snd_rpi_boomberry_digi_of_match);
++
++static struct platform_driver snd_rpi_boomberry_digi_driver = {
++ .driver = {
++ .name = "snd-rpi-boomberry-digi",
++ .owner = THIS_MODULE,
++ .of_match_table = snd_rpi_boomberry_digi_of_match,
++ },
++ .probe = snd_rpi_boomberry_digi_probe,
++ .remove = snd_rpi_boomberry_digi_remove,
++};
++
++module_platform_driver(snd_rpi_boomberry_digi_driver);
++
++MODULE_AUTHOR("Milan Neskovic <info@boomberry.co>");
++MODULE_DESCRIPTION("ASoC Driver for BoomBerry PI Digi HAT Sound Card");
++MODULE_LICENSE("GPL v2");
--- /dev/null
+From 51fa2dcacc44cddf74afa790dd5ffbfbbbfe0afc Mon Sep 17 00:00:00 2001
+From: Aaron Shaw <shawaj@gmail.com>
+Date: Fri, 8 Apr 2016 00:06:00 +0100
+Subject: [PATCH 242/304] Add support for mcp7940x family of RTC
+
+---
+ arch/arm/boot/dts/overlays/README | 2 ++
+ arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts | 6 ++++++
+ 2 files changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/overlays/README
++++ b/arch/arm/boot/dts/overlays/README
+@@ -435,6 +435,8 @@ Params: ds1307 Select t
+
+ ds3231 Select the DS3231 device
+
++ mcp7940x Select the MCP7940x device
++
+ mcp7941x Select the MCP7941x device
+
+ pcf2127 Select the PCF2127 device
+--- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts
++++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts
+@@ -23,6 +23,11 @@
+ reg = <0x68>;
+ status = "disable";
+ };
++ mcp7940x: mcp7940x@6f {
++ compatible = "microchip,mcp7940x";
++ reg = <0x6f>;
++ status = "disable";
++ };
+ mcp7941x: mcp7941x@6f {
+ compatible = "microchip,mcp7941x";
+ reg = <0x6f>;
+@@ -54,6 +59,7 @@
+ ds1307 = <&ds1307>,"status";
+ ds1339 = <&ds1339>,"status";
+ ds3231 = <&ds3231>,"status";
++ mcp7940x = <&mcp7940x>,"status";
+ mcp7941x = <&mcp7941x>,"status";
+ pcf2127 = <&pcf2127>,"status";
+ pcf8523 = <&pcf8523>,"status";
--- /dev/null
+From 162793500abf0310b5c9f2cf2bb3cf077390c065 Mon Sep 17 00:00:00 2001
+From: Jeremy McDermond <nh6z@nh6z.net>
+Date: Thu, 14 Apr 2016 09:39:20 -0700
+Subject: [PATCH 243/304] bcm2709_defconfig: Fix typo on BoomBerry
+ configuration directive
+
+The BoomBerry configuration directive in bcm2709_defconfig has a typo.
+---
+ arch/arm/configs/bcm2709_defconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/configs/bcm2709_defconfig
++++ b/arch/arm/configs/bcm2709_defconfig
+@@ -854,7 +854,7 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
+ CONFIG_SND_BCM2708_SOC_BOOMBERRY_DAC=m
+-CONFIG_SNG_BCM2708_SOC_BOOMBERRY_DIGI=m
++CONFIG_SND_BCM2708_SOC_BOOMBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_RPI_DAC=m
+ CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
+ CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
--- /dev/null
+From 62d7072d90d111836b7fcc57c3c2ff27faeeaee1 Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Fri, 15 Apr 2016 10:48:39 +0100
+Subject: [PATCH 244/304] boomberry-dac: Adjust for ALSA API change
+
+As of 4.4, snd_soc_limit_volume now takes a struct snd_soc_card *
+rather than a struct snd_soc_codec *.
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ sound/soc/bcm/boomberry-dac.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/sound/soc/bcm/boomberry-dac.c
++++ b/sound/soc/bcm/boomberry-dac.c
+@@ -40,9 +40,8 @@ static int snd_rpi_boomberry_dac_init(st
+ {
+ int ret;
+ struct snd_soc_card *card = rtd->card;
+- struct snd_soc_codec *codec = rtd->codec;
+
+- ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207);
++ ret = snd_soc_limit_volume(card, "Digital Playback Volume", 207);
+ if (ret < 0)
+ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret);
+ }
--- /dev/null
+From e513a9bd4cd878b982ee8ac9dd6942e550c77307 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Sun, 17 Apr 2016 04:44:47 -0700
+Subject: [PATCH 245/304] vmcs: Remove unused sm_cache_map_vector definition
+ (#1411)
+
+The code using it also ifdef'ed with 0, anyyd gcc 6
+complains
+
+error: 'sm_cache_map_vector' defined but not used
+
+The code using it also ifdef'ed out
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ drivers/char/broadcom/vc_sm/vmcs_sm.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/char/broadcom/vc_sm/vmcs_sm.c
++++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c
+@@ -197,12 +197,14 @@ struct SM_STATE_T {
+ static struct SM_STATE_T *sm_state;
+ static int sm_inited;
+
++#if 0
+ static const char *const sm_cache_map_vector[] = {
+ "(null)",
+ "host",
+ "videocore",
+ "host+videocore",
+ };
++#endif
+
+ /* ---- Private Function Prototypes -------------------------------------- */
+
--- /dev/null
+From 3c64edb93a4702adc85dc1284a83d8c66ad850bf Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Mon, 18 Apr 2016 11:56:53 +0100
+Subject: [PATCH 246/304] scripts/mkknlimg: Append a trailer for all input
+
+Now that the firmware assumes an unsigned kernel is DT-capable, it is
+helpful to be able to mark a kernel as being non-DT-capable.
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ scripts/mkknlimg | 11 +++++------
+ 1 file changed, 5 insertions(+), 6 deletions(-)
+
+--- a/scripts/mkknlimg
++++ b/scripts/mkknlimg
+@@ -98,7 +98,7 @@ my $append_trailer;
+ my $trailer;
+ my $kver = '?';
+
+-$append_trailer = $dtok;
++$append_trailer = 1;
+
+ if ($res)
+ {
+@@ -108,7 +108,6 @@ if ($res)
+
+ if ($flags & FLAG_PI)
+ {
+- $append_trailer = 1;
+ $dtok ||= ($flags & FLAG_DTOK) != 0;
+ $is_270x ||= ($flags & FLAG_270X) != 0;
+ $is_283x ||= ($flags & FLAG_283X) != 0;
+@@ -116,18 +115,18 @@ if ($res)
+ }
+ else
+ {
+- print ("* This doesn't look like a Raspberry Pi kernel. In pass-through mode.\n");
++ print ("* This doesn't look like a Raspberry Pi kernel.\n");
+ }
+ }
+ elsif (!$dtok)
+ {
+- print ("* Is this a valid kernel? In pass-through mode.\n");
++ print ("* Is this a valid kernel?\n");
+ }
+
+ if ($append_trailer)
+ {
+ printf("DT: %s\n", $dtok ? "y" : "n");
+- printf("DDT: %s\n", $ddtk ? "y" : "n") if ($ddtk);
++ printf("DDT: %s\n", $ddtk ? "y" : "n");
+ printf("270x: %s\n", $is_270x ? "y" : "n");
+ printf("283x: %s\n", $is_283x ? "y" : "n");
+
+@@ -136,7 +135,7 @@ if ($append_trailer)
+ push @atoms, [ $trailer_magic, pack('V', 0) ];
+ push @atoms, [ 'KVer', $kver ];
+ push @atoms, [ 'DTOK', pack('V', $dtok) ];
+- push @atoms, [ 'DDTK', pack('V', $ddtk) ] if ($ddtk);
++ push @atoms, [ 'DDTK', pack('V', $ddtk) ];
+ push @atoms, [ '270X', pack('V', $is_270x) ];
+ push @atoms, [ '283X', pack('V', $is_283x) ];
+ push @atoms, [ '283x', pack('V', $is_283x && !$is_270x) ];
--- /dev/null
+From 16dced270b5dbcafa2d26096733c64a2f3e75071 Mon Sep 17 00:00:00 2001
+From: popcornmix <popcornmix@gmail.com>
+Date: Tue, 19 Apr 2016 12:57:52 +0100
+Subject: [PATCH 247/304] bcm2835_thermal: Don't report unsupported trip type
+
+---
+ drivers/thermal/bcm2835-thermal.c | 34 +---------------------------------
+ 1 file changed, 1 insertion(+), 33 deletions(-)
+
+--- a/drivers/thermal/bcm2835-thermal.c
++++ b/drivers/thermal/bcm2835-thermal.c
+@@ -49,38 +49,8 @@ static int bcm2835_thermal_get_temp(stru
+ RPI_FIRMWARE_GET_TEMPERATURE);
+ }
+
+-static int bcm2835_thermal_get_max_temp(struct thermal_zone_device *tz,
+- int trip, int *temp)
+-{
+- /*
+- * The maximum safe temperature of the SoC.
+- * Overclock may be disabled above this temperature.
+- */
+- return bcm2835_thermal_get_property(tz, temp,
+- RPI_FIRMWARE_GET_MAX_TEMPERATURE);
+-}
+-
+-static int bcm2835_thermal_get_trip_type(struct thermal_zone_device *tz,
+- int trip, enum thermal_trip_type *type)
+-{
+- *type = THERMAL_TRIP_HOT;
+-
+- return 0;
+-}
+-
+-static int bcm2835_thermal_get_mode(struct thermal_zone_device *tz,
+- enum thermal_device_mode *mode)
+-{
+- *mode = THERMAL_DEVICE_ENABLED;
+-
+- return 0;
+-}
+-
+ static struct thermal_zone_device_ops ops = {
+ .get_temp = bcm2835_thermal_get_temp,
+- .get_trip_temp = bcm2835_thermal_get_max_temp,
+- .get_trip_type = bcm2835_thermal_get_trip_type,
+- .get_mode = bcm2835_thermal_get_mode,
+ };
+
+ static int bcm2835_thermal_probe(struct platform_device *pdev)
+@@ -90,17 +60,15 @@ static int bcm2835_thermal_probe(struct
+ struct thermal_zone_device *tz;
+
+ fw_np = of_parse_phandle(pdev->dev.of_node, "firmware", 0);
+-/* Remove comment when booting without Device Tree is no longer supported
+ if (!fw_np) {
+ dev_err(&pdev->dev, "Missing firmware node\n");
+ return -ENOENT;
+ }
+-*/
+ fw = rpi_firmware_get(fw_np);
+ if (!fw)
+ return -EPROBE_DEFER;
+
+- tz = thermal_zone_device_register("bcm2835_thermal", 1, 0, fw, &ops,
++ tz = thermal_zone_device_register("bcm2835_thermal", 0, 0, fw, &ops,
+ NULL, 0, 0);
+ if (IS_ERR(tz)) {
+ dev_err(&pdev->dev, "Failed to register the thermal device\n");
--- /dev/null
+From b617c25e48308f1901af150a9bc544254416d3c8 Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Tue, 19 Apr 2016 13:55:29 +0100
+Subject: [PATCH 248/304] scripts/dtc: Only emit local fixups for overlays
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ scripts/dtc/checks.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/scripts/dtc/checks.c
++++ b/scripts/dtc/checks.c
+@@ -514,7 +514,7 @@ static void fixup_phandle_references(str
+ }
+
+ /* if it's a local reference, we need to record it */
+- if (symbol_fixup_support) {
++ if (symbol_fixup_support && dt->is_plugin) {
+
+ /* allocate a new local fixup entry */
+ fe = xmalloc(sizeof(*fe));
--- /dev/null
+From 74f05075c9f20865651019acc76ac0cf957eebbf Mon Sep 17 00:00:00 2001
+From: wm4 <wm4@nowhere>
+Date: Tue, 19 Apr 2016 16:08:35 +0200
+Subject: [PATCH 249/304] bcm2835: do not require substream for accessing chmap
+ ctl
+
+Fixes alsasctl store/restore operation.
+---
+ sound/arm/bcm2835-ctl.c | 10 +---------
+ 1 file changed, 1 insertion(+), 9 deletions(-)
+
+--- a/sound/arm/bcm2835-ctl.c
++++ b/sound/arm/bcm2835-ctl.c
+@@ -489,8 +489,6 @@ static int snd_bcm2835_chmap_ctl_get(str
+ {
+ struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
+ bcm2835_chip_t *chip = info->private_data;
+- unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
+- struct snd_pcm_substream *substream = snd_pcm_chmap_substream(info, idx);
+ struct cea_channel_speaker_allocation *ch = NULL;
+ int res = 0;
+ int cur = 0;
+@@ -499,11 +497,6 @@ static int snd_bcm2835_chmap_ctl_get(str
+ if (mutex_lock_interruptible(&chip->audio_mutex))
+ return -EINTR;
+
+- if (!substream || !substream->runtime) {
+- res = -ENODEV;
+- goto unlock;
+- }
+-
+ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
+ if (channel_allocations[i].ca_index == chip->cea_chmap)
+ ch = &channel_allocations[i];
+@@ -521,7 +514,6 @@ static int snd_bcm2835_chmap_ctl_get(str
+ while (cur < 8)
+ ucontrol->value.integer.value[cur++] = SNDRV_CHMAP_NA;
+
+-unlock:
+ mutex_unlock(&chip->audio_mutex);
+ return res;
+ }
+@@ -541,7 +533,7 @@ static int snd_bcm2835_chmap_ctl_put(str
+ return -EINTR;
+
+ if (!substream || !substream->runtime) {
+- res = -ENODEV;
++ /* ignore and return success for the sake of alsactl */
+ goto unlock;
+ }
+
--- /dev/null
+From 15d5b6a4a03c90b653719978831dc97633c6e332 Mon Sep 17 00:00:00 2001
+From: wm4 <wm4@nowhere>
+Date: Tue, 19 Apr 2016 16:29:41 +0200
+Subject: [PATCH 250/304] bcm2835: add fallback channel layouts if channel map
+ API is not used
+
+Should be more useful than just forcing stereo.
+
+We can't match the exact legacy ALSA channel layouts, so this is a
+"best effort" hack.
+
+I'm not sure what happens if the application requests channel counts
+that are not power-of-2s. The channel map API hopefully forces
+applications which use the channel map API to request the correct
+count by adding padding channels, but the bare API enforces
+nothing. Possibly this could be added to rate_hw_constraint_channels
+at a later point.
+---
+ sound/arm/bcm2835-vchiq.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+--- a/sound/arm/bcm2835-vchiq.c
++++ b/sound/arm/bcm2835-vchiq.c
+@@ -598,7 +598,16 @@ int bcm2835_audio_set_params(bcm2835_als
+ if (alsa_stream->chip->cea_chmap >= 0) {
+ chmap_value = (unsigned)alsa_stream->chip->cea_chmap << 24;
+ } else {
+- chmap_value = 0; /* force stereo */
++ /* fallback layouts for applications which do not use chmap API */
++ chmap_value = 0x00;
++ switch (channels) {
++ case 3: chmap_value = 0x01; break;
++ case 4: chmap_value = 0x03; break;
++ case 5: chmap_value = 0x07; break;
++ case 6: chmap_value = 0x0b; break;
++ case 7: chmap_value = 0x0f; break;
++ case 8: chmap_value = 0x13; break;
++ }
+ for (i = 0; i < 8; i++)
+ alsa_stream->chip->map_channels[i] = i;
+ }
--- /dev/null
+From 0307b1dc72eb904e3e81b82050070e8bcfec6e01 Mon Sep 17 00:00:00 2001
+From: wm4 <wm4@nowhere>
+Date: Tue, 19 Apr 2016 16:38:03 +0200
+Subject: [PATCH 251/304] bcm2835: log which channel map is set
+
+---
+ sound/arm/bcm2835-vchiq.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/sound/arm/bcm2835-vchiq.c
++++ b/sound/arm/bcm2835-vchiq.c
+@@ -596,8 +596,11 @@ int bcm2835_audio_set_params(bcm2835_als
+ instance->result = -1;
+
+ if (alsa_stream->chip->cea_chmap >= 0) {
++ LOG_INFO("Using application requested channel map: %d\n",
++ alsa_stream->chip->cea_chmap);
+ chmap_value = (unsigned)alsa_stream->chip->cea_chmap << 24;
+ } else {
++ LOG_INFO("Using fallback channel map.\n");
+ /* fallback layouts for applications which do not use chmap API */
+ chmap_value = 0x00;
+ switch (channels) {
+@@ -614,6 +617,8 @@ int bcm2835_audio_set_params(bcm2835_als
+ for (i = 0; i < 8; i++)
+ chmap_value |= alsa_stream->chip->map_channels[i] << (i * 3);
+
++ LOG_INFO("Requesting AUDS channel map: 0x%lx\n", (long)chmap_value);
++
+ m.type = VC_AUDIO_MSG_TYPE_CONFIG;
+ m.u.config.channels = channels;
+ m.u.config.samplerate = samplerate;
--- /dev/null
+From 78c280c96a984805dfa19969e927c17ccada808f Mon Sep 17 00:00:00 2001
+From: Remi Pommarel <repk@triplefau.lt>
+Date: Sun, 6 Dec 2015 17:22:46 +0100
+Subject: [PATCH 252/304] clk: bcm2835: add a round up ability to the clock
+ divisor
+
+Make bcm2835_clock_choose_div to optionally round up the chosen MASH divisor
+so that the resulting average rate will not be higher than the requested one.
+
+Signed-off-by: Remi Pommarel <repk@triplefau.lt>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Michael Turquette <mturquette@baylibre.com>
+(cherry picked from commit 9c95b32ca09364e4687b72c4e17b78dc1c420026)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 22 ++++++++++++----------
+ 1 file changed, 12 insertions(+), 10 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1150,22 +1150,24 @@ static int bcm2835_clock_is_on(struct cl
+
+ static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
+ unsigned long rate,
+- unsigned long parent_rate)
++ unsigned long parent_rate,
++ bool round_up)
+ {
+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
+ const struct bcm2835_clock_data *data = clock->data;
+- u32 unused_frac_mask = GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0);
++ u32 unused_frac_mask =
++ GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
+ u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
++ u64 rem;
+ u32 div;
+
+- do_div(temp, rate);
++ rem = do_div(temp, rate);
+ div = temp;
+
+- /* Round and mask off the unused bits */
+- if (unused_frac_mask != 0) {
+- div += unused_frac_mask >> 1;
+- div &= ~unused_frac_mask;
+- }
++ /* Round up and mask off the unused bits */
++ if (round_up && ((div & unused_frac_mask) != 0 || rem != 0))
++ div += unused_frac_mask + 1;
++ div &= ~unused_frac_mask;
+
+ /* Clamp to the limits. */
+ div = max(div, unused_frac_mask + 1);
+@@ -1204,7 +1206,7 @@ static long bcm2835_clock_round_rate(str
+ unsigned long *parent_rate)
+ {
+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
+- u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate);
++ u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate, false);
+
+ return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);
+ }
+@@ -1273,7 +1275,7 @@ static int bcm2835_clock_set_rate(struct
+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
+ struct bcm2835_cprman *cprman = clock->cprman;
+ const struct bcm2835_clock_data *data = clock->data;
+- u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
++ u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
+
+ cprman_write(cprman, data->div_reg, div);
+
--- /dev/null
+From f875d2424d83a76d4b3942263291917853d56158 Mon Sep 17 00:00:00 2001
+From: Remi Pommarel <repk@triplefau.lt>
+Date: Sun, 6 Dec 2015 17:22:47 +0100
+Subject: [PATCH 253/304] clk: bcm2835: Support for clock parent selection
+
+Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple
+parent clocks. These clocks divide the rate of a parent which can be selected by
+setting the proper bits in the clock control register.
+
+Previously all these parents where handled by a mux clock. But a mux clock
+cannot be used because updating clock control register to select parent needs a
+password to be xor'd with the parent index.
+
+This patch get rid of mux clock and make these clocks handle their own parent,
+allowing them to select the one to use.
+
+Signed-off-by: Remi Pommarel <repk@triplefau.lt>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Michael Turquette <mturquette@baylibre.com>
+(cherry picked from commit 6d18b8adbe679b5947aa822b676efff230acc5f6)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 122 ++++++++++++++++++++++++++----------------
+ 1 file changed, 77 insertions(+), 45 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1201,16 +1201,6 @@ static long bcm2835_clock_rate_from_divi
+ return temp;
+ }
+
+-static long bcm2835_clock_round_rate(struct clk_hw *hw,
+- unsigned long rate,
+- unsigned long *parent_rate)
+-{
+- struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
+- u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate, false);
+-
+- return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);
+-}
+-
+ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+ {
+@@ -1282,13 +1272,75 @@ static int bcm2835_clock_set_rate(struct
+ return 0;
+ }
+
++static int bcm2835_clock_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
++ struct clk_hw *parent, *best_parent = NULL;
++ unsigned long rate, best_rate = 0;
++ unsigned long prate, best_prate = 0;
++ size_t i;
++ u32 div;
++
++ /*
++ * Select parent clock that results in the closest but lower rate
++ */
++ for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
++ parent = clk_hw_get_parent_by_index(hw, i);
++ if (!parent)
++ continue;
++ prate = clk_hw_get_rate(parent);
++ div = bcm2835_clock_choose_div(hw, req->rate, prate, true);
++ rate = bcm2835_clock_rate_from_divisor(clock, prate, div);
++ if (rate > best_rate && rate <= req->rate) {
++ best_parent = parent;
++ best_prate = prate;
++ best_rate = rate;
++ }
++ }
++
++ if (!best_parent)
++ return -EINVAL;
++
++ req->best_parent_hw = best_parent;
++ req->best_parent_rate = best_prate;
++
++ req->rate = best_rate;
++
++ return 0;
++}
++
++static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
++{
++ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
++ struct bcm2835_cprman *cprman = clock->cprman;
++ const struct bcm2835_clock_data *data = clock->data;
++ u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
++
++ cprman_write(cprman, data->ctl_reg, src);
++ return 0;
++}
++
++static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
++{
++ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
++ struct bcm2835_cprman *cprman = clock->cprman;
++ const struct bcm2835_clock_data *data = clock->data;
++ u32 src = cprman_read(cprman, data->ctl_reg);
++
++ return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
++}
++
++
+ static const struct clk_ops bcm2835_clock_clk_ops = {
+ .is_prepared = bcm2835_clock_is_on,
+ .prepare = bcm2835_clock_on,
+ .unprepare = bcm2835_clock_off,
+ .recalc_rate = bcm2835_clock_get_rate,
+ .set_rate = bcm2835_clock_set_rate,
+- .round_rate = bcm2835_clock_round_rate,
++ .determine_rate = bcm2835_clock_determine_rate,
++ .set_parent = bcm2835_clock_set_parent,
++ .get_parent = bcm2835_clock_get_parent,
+ };
+
+ static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
+@@ -1304,7 +1356,9 @@ static const struct clk_ops bcm2835_vpu_
+ .is_prepared = bcm2835_vpu_clock_is_on,
+ .recalc_rate = bcm2835_clock_get_rate,
+ .set_rate = bcm2835_clock_set_rate,
+- .round_rate = bcm2835_clock_round_rate,
++ .determine_rate = bcm2835_clock_determine_rate,
++ .set_parent = bcm2835_clock_set_parent,
++ .get_parent = bcm2835_clock_get_parent,
+ };
+
+ static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman,
+@@ -1398,45 +1452,23 @@ static struct clk *bcm2835_register_cloc
+ {
+ struct bcm2835_clock *clock;
+ struct clk_init_data init;
+- const char *parent;
++ const char *parents[1 << CM_SRC_BITS];
++ size_t i;
+
+ /*
+- * Most of the clock generators have a mux field, so we
+- * instantiate a generic mux as our parent to handle it.
++ * Replace our "xosc" references with the oscillator's
++ * actual name.
+ */
+- if (data->num_mux_parents) {
+- const char *parents[1 << CM_SRC_BITS];
+- int i;
+-
+- parent = devm_kasprintf(cprman->dev, GFP_KERNEL,
+- "mux_%s", data->name);
+- if (!parent)
+- return NULL;
+-
+- /*
+- * Replace our "xosc" references with the oscillator's
+- * actual name.
+- */
+- for (i = 0; i < data->num_mux_parents; i++) {
+- if (strcmp(data->parents[i], "xosc") == 0)
+- parents[i] = cprman->osc_name;
+- else
+- parents[i] = data->parents[i];
+- }
+-
+- clk_register_mux(cprman->dev, parent,
+- parents, data->num_mux_parents,
+- CLK_SET_RATE_PARENT,
+- cprman->regs + data->ctl_reg,
+- CM_SRC_SHIFT, CM_SRC_BITS,
+- 0, &cprman->regs_lock);
+- } else {
+- parent = data->parents[0];
++ for (i = 0; i < data->num_mux_parents; i++) {
++ if (strcmp(data->parents[i], "xosc") == 0)
++ parents[i] = cprman->osc_name;
++ else
++ parents[i] = data->parents[i];
+ }
+
+ memset(&init, 0, sizeof(init));
+- init.parent_names = &parent;
+- init.num_parents = 1;
++ init.parent_names = parents;
++ init.num_parents = data->num_mux_parents;
+ init.name = data->name;
+ init.flags = CLK_IGNORE_UNUSED;
+
--- /dev/null
+From 356488d8d56d35fe7316d829d1bfc7a7ec362d6c Mon Sep 17 00:00:00 2001
+From: Remi Pommarel <repk@triplefau.lt>
+Date: Sun, 6 Dec 2015 17:22:48 +0100
+Subject: [PATCH 254/304] clk: bcm2835: Add PWM clock support
+
+Register the pwm clock for bcm2835.
+
+Signed-off-by: Remi Pommarel <repk@triplefau.lt>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Michael Turquette <mturquette@baylibre.com>
+(cherry picked from commit cfbab8fbab9c330aca963095a439c451ac97c0dd)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 13 +++++++++++++
+ include/dt-bindings/clock/bcm2835.h | 3 ++-
+ 2 files changed, 15 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -807,6 +807,16 @@ static const struct bcm2835_clock_data b
+ .frac_bits = 8,
+ };
+
++static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
++ .name = "pwm",
++ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
++ .parents = bcm2835_clock_per_parents,
++ .ctl_reg = CM_PWMCTL,
++ .div_reg = CM_PWMDIV,
++ .int_bits = 12,
++ .frac_bits = 12,
++};
++
+ struct bcm2835_pll {
+ struct clk_hw hw;
+ struct bcm2835_cprman *cprman;
+@@ -1586,6 +1596,9 @@ static int bcm2835_clk_probe(struct plat
+ cprman->regs + CM_PERIICTL, CM_GATE_BIT,
+ 0, &cprman->regs_lock);
+
++ clks[BCM2835_CLOCK_PWM] =
++ bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
++
+ return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
+ &cprman->onecell);
+ }
+--- a/include/dt-bindings/clock/bcm2835.h
++++ b/include/dt-bindings/clock/bcm2835.h
+@@ -43,5 +43,6 @@
+ #define BCM2835_CLOCK_TSENS 27
+ #define BCM2835_CLOCK_EMMC 28
+ #define BCM2835_CLOCK_PERI_IMAGE 29
++#define BCM2835_CLOCK_PWM 30
+
+-#define BCM2835_CLOCK_COUNT 30
++#define BCM2835_CLOCK_COUNT 31
--- /dev/null
+From de5c22eb349acaa6772dec9c0d56faa1d53932c1 Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Tue, 22 Dec 2015 20:13:08 +0000
+Subject: [PATCH 255/304] clk: bcm2835: added missing clock register
+ definitions
+
+Added missing CTRL and DIV clock register definitions for:
+PCM, SLIM, TCNT, TEC, TD0, TD1
+
+Register information taken from:
+https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM
+which extracted the information from the header files shared by
+Broadcom/rpi foundation in this file:
+http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+(cherry picked from commit 2103a2156119b30f5924af2a1094227954be4617)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -88,10 +88,23 @@
+ #define CM_HSMDIV 0x08c
+ #define CM_OTPCTL 0x090
+ #define CM_OTPDIV 0x094
++#define CM_PCMCTL 0x098
++#define CM_PCMDIV 0x09c
+ #define CM_PWMCTL 0x0a0
+ #define CM_PWMDIV 0x0a4
++#define CM_SLIMCTL 0x0a8
++#define CM_SLIMDIV 0x0ac
+ #define CM_SMICTL 0x0b0
+ #define CM_SMIDIV 0x0b4
++/* no definition for 0x0b8 and 0x0bc */
++#define CM_TCNTCTL 0x0c0
++#define CM_TCNTDIV 0x0c4
++#define CM_TECCTL 0x0c8
++#define CM_TECDIV 0x0cc
++#define CM_TD0CTL 0x0d0
++#define CM_TD0DIV 0x0d4
++#define CM_TD1CTL 0x0d8
++#define CM_TD1DIV 0x0dc
+ #define CM_TSENSCTL 0x0e0
+ #define CM_TSENSDIV 0x0e4
+ #define CM_TIMERCTL 0x0e8
--- /dev/null
+From 2083f21dc65df8ce4fd887acd815551058b23e3e Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 11:39:17 +0000
+Subject: [PATCH 256/304] clk: bcm2835: pll_off should only update
+ CM_PLL_ANARST
+
+bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
+register, which may lose the other bits that are currently set by the
+clock dividers.
+
+It also now locks during the read/modify/write cycle of both
+registers.
+
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
+audio domain clocks")
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 6727f086cfe4ddcc651eb2bf4301abfcf619be06)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -913,8 +913,14 @@ static void bcm2835_pll_off(struct clk_h
+ struct bcm2835_cprman *cprman = pll->cprman;
+ const struct bcm2835_pll_data *data = pll->data;
+
+- cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
+- cprman_write(cprman, data->a2w_ctrl_reg, A2W_PLL_CTRL_PWRDN);
++ spin_lock(&cprman->regs_lock);
++ cprman_write(cprman, data->cm_ctrl_reg,
++ cprman_read(cprman, data->cm_ctrl_reg) |
++ CM_PLL_ANARST);
++ cprman_write(cprman, data->a2w_ctrl_reg,
++ cprman_read(cprman, data->a2w_ctrl_reg) |
++ A2W_PLL_CTRL_PWRDN);
++ spin_unlock(&cprman->regs_lock);
+ }
+
+ static int bcm2835_pll_on(struct clk_hw *hw)
--- /dev/null
+From 39c3c0d0a8d038a692b95cc13e7d6acf2d04cf14 Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 11:39:18 +0000
+Subject: [PATCH 257/304] clk: bcm2835: add locking to pll*_on/off methods
+
+Add missing locking to:
+* bcm2835_pll_divider_on
+* bcm2835_pll_divider_off
+to protect the read modify write cycle for the
+register access protecting both cm_reg and a2w_reg
+registers.
+
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
+audio domain clocks")
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit ec36a5c6682fdd5328abf15c3c67281bed0241d7)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1097,10 +1097,12 @@ static void bcm2835_pll_divider_off(stru
+ struct bcm2835_cprman *cprman = divider->cprman;
+ const struct bcm2835_pll_divider_data *data = divider->data;
+
++ spin_lock(&cprman->regs_lock);
+ cprman_write(cprman, data->cm_reg,
+ (cprman_read(cprman, data->cm_reg) &
+ ~data->load_mask) | data->hold_mask);
+ cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE);
++ spin_unlock(&cprman->regs_lock);
+ }
+
+ static int bcm2835_pll_divider_on(struct clk_hw *hw)
+@@ -1109,12 +1111,14 @@ static int bcm2835_pll_divider_on(struct
+ struct bcm2835_cprman *cprman = divider->cprman;
+ const struct bcm2835_pll_divider_data *data = divider->data;
+
++ spin_lock(&cprman->regs_lock);
+ cprman_write(cprman, data->a2w_reg,
+ cprman_read(cprman, data->a2w_reg) &
+ ~A2W_PLL_CHANNEL_DISABLE);
+
+ cprman_write(cprman, data->cm_reg,
+ cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
++ spin_unlock(&cprman->regs_lock);
+
+ return 0;
+ }
--- /dev/null
+From 54eece496d38fb701d9719169d9270d8798191cc Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 11:39:20 +0000
+Subject: [PATCH 258/304] clk: bcm2835: divider value has to be 1 or more
+
+Current clamping of a normal divider allows a value < 1 to be valid.
+
+A divider of < 1 would actually only be possible if we had a PLL...
+
+So this patch clamps the divider to 1.
+
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
+audio domain clocks")
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1202,8 +1202,9 @@ static u32 bcm2835_clock_choose_div(stru
+ div += unused_frac_mask + 1;
+ div &= ~unused_frac_mask;
+
+- /* Clamp to the limits. */
+- div = max(div, unused_frac_mask + 1);
++ /* clamp to min divider of 1 */
++ div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
++ /* clamp to the highest possible fractional divider */
+ div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
+ CM_DIV_FRAC_BITS - data->frac_bits));
+
--- /dev/null
+From c69411a2204c088d6a695c00a7e09fac0f8c0b89 Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 11:39:21 +0000
+Subject: [PATCH 259/304] clk: bcm2835: correctly enable fractional clock
+ support
+
+The current driver calculates the clock divider with
+fractional support enabled.
+
+But it does not enable fractional support in the
+control register itself resulting in an integer only divider,
+but in clk_set_rate responds back the fractionally divided
+clock frequency.
+
+This patch enables fractional support in the control register
+whenever there is a fractional bit set in the requested clock divider.
+
+Mash clock limits are are also handled for the PWM clock
+applying the correct divider limits (2 and max_int) applicable to
+basic fractional divider support (mash order of 1).
+
+It also adds locking to protect the read/modify/write cycle of
+the register modification.
+
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
+audio domain clocks")
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 959ca92a3235fc4b17c1e18483fc390b3d612254)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 45 +++++++++++++++++++++++++++++++++++++------
+ 1 file changed, 39 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -51,6 +51,7 @@
+ #define CM_GNRICCTL 0x000
+ #define CM_GNRICDIV 0x004
+ # define CM_DIV_FRAC_BITS 12
++# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
+
+ #define CM_VPUCTL 0x008
+ #define CM_VPUDIV 0x00c
+@@ -128,6 +129,7 @@
+ # define CM_GATE BIT(CM_GATE_BIT)
+ # define CM_BUSY BIT(7)
+ # define CM_BUSYD BIT(8)
++# define CM_FRAC BIT(9)
+ # define CM_SRC_SHIFT 0
+ # define CM_SRC_BITS 4
+ # define CM_SRC_MASK 0xf
+@@ -647,6 +649,7 @@ struct bcm2835_clock_data {
+ u32 frac_bits;
+
+ bool is_vpu_clock;
++ bool is_mash_clock;
+ };
+
+ static const char *const bcm2835_clock_per_parents[] = {
+@@ -828,6 +831,7 @@ static const struct bcm2835_clock_data b
+ .div_reg = CM_PWMDIV,
+ .int_bits = 12,
+ .frac_bits = 12,
++ .is_mash_clock = true,
+ };
+
+ struct bcm2835_pll {
+@@ -1192,7 +1196,7 @@ static u32 bcm2835_clock_choose_div(stru
+ GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
+ u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
+ u64 rem;
+- u32 div;
++ u32 div, mindiv, maxdiv;
+
+ rem = do_div(temp, rate);
+ div = temp;
+@@ -1202,11 +1206,23 @@ static u32 bcm2835_clock_choose_div(stru
+ div += unused_frac_mask + 1;
+ div &= ~unused_frac_mask;
+
+- /* clamp to min divider of 1 */
+- div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
+- /* clamp to the highest possible fractional divider */
+- div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
+- CM_DIV_FRAC_BITS - data->frac_bits));
++ /* different clamping limits apply for a mash clock */
++ if (data->is_mash_clock) {
++ /* clamp to min divider of 2 */
++ mindiv = 2 << CM_DIV_FRAC_BITS;
++ /* clamp to the highest possible integer divider */
++ maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
++ } else {
++ /* clamp to min divider of 1 */
++ mindiv = 1 << CM_DIV_FRAC_BITS;
++ /* clamp to the highest possible fractional divider */
++ maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
++ CM_DIV_FRAC_BITS - data->frac_bits);
++ }
++
++ /* apply the clamping limits */
++ div = max_t(u32, div, mindiv);
++ div = min_t(u32, div, maxdiv);
+
+ return div;
+ }
+@@ -1300,9 +1316,26 @@ static int bcm2835_clock_set_rate(struct
+ struct bcm2835_cprman *cprman = clock->cprman;
+ const struct bcm2835_clock_data *data = clock->data;
+ u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
++ u32 ctl;
++
++ spin_lock(&cprman->regs_lock);
++
++ /*
++ * Setting up frac support
++ *
++ * In principle it is recommended to stop/start the clock first,
++ * but as we set CLK_SET_RATE_GATE during registration of the
++ * clock this requirement should be take care of by the
++ * clk-framework.
++ */
++ ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
++ ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
++ cprman_write(cprman, data->ctl_reg, ctl);
+
+ cprman_write(cprman, data->div_reg, div);
+
++ spin_unlock(&cprman->regs_lock);
++
+ return 0;
+ }
+
--- /dev/null
+From 6bdeaf1c6d46819acb01de258574759e21f021d1 Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 11:39:22 +0000
+Subject: [PATCH 260/304] clk: bcm2835: clean up coding style issues
+
+Fix all the checkpatch complaints for clk-bcm2835.c
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 6e1e60dacee7b32aef1468ea461b02e4c7a90a45)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -12,9 +12,6 @@
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+ /**
+@@ -299,7 +296,7 @@
+ struct bcm2835_cprman {
+ struct device *dev;
+ void __iomem *regs;
+- spinlock_t regs_lock;
++ spinlock_t regs_lock; /* spinlock for all clocks */
+ const char *osc_name;
+
+ struct clk_onecell_data onecell;
+@@ -1340,7 +1337,7 @@ static int bcm2835_clock_set_rate(struct
+ }
+
+ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
+- struct clk_rate_request *req)
++ struct clk_rate_request *req)
+ {
+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
+ struct clk_hw *parent, *best_parent = NULL;
+@@ -1398,7 +1395,6 @@ static u8 bcm2835_clock_get_parent(struc
+ return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
+ }
+
+-
+ static const struct clk_ops bcm2835_clock_clk_ops = {
+ .is_prepared = bcm2835_clock_is_on,
+ .prepare = bcm2835_clock_on,
--- /dev/null
+From 4da1c0d401cb719b7347117c226f4d4d95797972 Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 14:20:15 +0000
+Subject: [PATCH 261/304] clk: bcm2835: expose raw clock-registers via debugfs
+
+For debugging purposes under some circumstance
+it helps to be able to see the actual clock registers.
+
+E.g: when looking at the clock divider it is helpful to
+see what the actual clock divider is.
+
+This patch exposes all the clock registers specific to each
+clock/pll/pll-divider via debugfs.
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Acked-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 96bf9c69d5729781018a00f08e2ae395ec3346b4)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 101 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 101 insertions(+)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -37,6 +37,7 @@
+ #include <linux/clk-provider.h>
+ #include <linux/clkdev.h>
+ #include <linux/clk/bcm2835.h>
++#include <linux/debugfs.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+@@ -313,6 +314,27 @@ static inline u32 cprman_read(struct bcm
+ return readl(cprman->regs + reg);
+ }
+
++static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
++ struct debugfs_reg32 *regs, size_t nregs,
++ struct dentry *dentry)
++{
++ struct dentry *regdump;
++ struct debugfs_regset32 *regset;
++
++ regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
++ if (!regset)
++ return -ENOMEM;
++
++ regset->regs = regs;
++ regset->nregs = nregs;
++ regset->base = cprman->regs + base;
++
++ regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry,
++ regset);
++
++ return regdump ? 0 : -ENOMEM;
++}
++
+ /*
+ * These are fixed clocks. They're probably not all root clocks and it may
+ * be possible to turn them on and off but until this is mapped out better
+@@ -1040,6 +1062,36 @@ static int bcm2835_pll_set_rate(struct c
+ return 0;
+ }
+
++static int bcm2835_pll_debug_init(struct clk_hw *hw,
++ struct dentry *dentry)
++{
++ struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
++ struct bcm2835_cprman *cprman = pll->cprman;
++ const struct bcm2835_pll_data *data = pll->data;
++ struct debugfs_reg32 *regs;
++
++ regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
++ if (!regs)
++ return -ENOMEM;
++
++ regs[0].name = "cm_ctrl";
++ regs[0].offset = data->cm_ctrl_reg;
++ regs[1].name = "a2w_ctrl";
++ regs[1].offset = data->a2w_ctrl_reg;
++ regs[2].name = "frac";
++ regs[2].offset = data->frac_reg;
++ regs[3].name = "ana0";
++ regs[3].offset = data->ana_reg_base + 0 * 4;
++ regs[4].name = "ana1";
++ regs[4].offset = data->ana_reg_base + 1 * 4;
++ regs[5].name = "ana2";
++ regs[5].offset = data->ana_reg_base + 2 * 4;
++ regs[6].name = "ana3";
++ regs[6].offset = data->ana_reg_base + 3 * 4;
++
++ return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
++}
++
+ static const struct clk_ops bcm2835_pll_clk_ops = {
+ .is_prepared = bcm2835_pll_is_on,
+ .prepare = bcm2835_pll_on,
+@@ -1047,6 +1099,7 @@ static const struct clk_ops bcm2835_pll_
+ .recalc_rate = bcm2835_pll_get_rate,
+ .set_rate = bcm2835_pll_set_rate,
+ .round_rate = bcm2835_pll_round_rate,
++ .debug_init = bcm2835_pll_debug_init,
+ };
+
+ struct bcm2835_pll_divider {
+@@ -1147,6 +1200,26 @@ static int bcm2835_pll_divider_set_rate(
+ return 0;
+ }
+
++static int bcm2835_pll_divider_debug_init(struct clk_hw *hw,
++ struct dentry *dentry)
++{
++ struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
++ struct bcm2835_cprman *cprman = divider->cprman;
++ const struct bcm2835_pll_divider_data *data = divider->data;
++ struct debugfs_reg32 *regs;
++
++ regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL);
++ if (!regs)
++ return -ENOMEM;
++
++ regs[0].name = "cm";
++ regs[0].offset = data->cm_reg;
++ regs[1].name = "a2w";
++ regs[1].offset = data->a2w_reg;
++
++ return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
++}
++
+ static const struct clk_ops bcm2835_pll_divider_clk_ops = {
+ .is_prepared = bcm2835_pll_divider_is_on,
+ .prepare = bcm2835_pll_divider_on,
+@@ -1154,6 +1227,7 @@ static const struct clk_ops bcm2835_pll_
+ .recalc_rate = bcm2835_pll_divider_get_rate,
+ .set_rate = bcm2835_pll_divider_set_rate,
+ .round_rate = bcm2835_pll_divider_round_rate,
++ .debug_init = bcm2835_pll_divider_debug_init,
+ };
+
+ /*
+@@ -1395,6 +1469,31 @@ static u8 bcm2835_clock_get_parent(struc
+ return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
+ }
+
++static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
++ {
++ .name = "ctl",
++ .offset = 0,
++ },
++ {
++ .name = "div",
++ .offset = 4,
++ },
++};
++
++static int bcm2835_clock_debug_init(struct clk_hw *hw,
++ struct dentry *dentry)
++{
++ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
++ struct bcm2835_cprman *cprman = clock->cprman;
++ const struct bcm2835_clock_data *data = clock->data;
++
++ return bcm2835_debugfs_regset(
++ cprman, data->ctl_reg,
++ bcm2835_debugfs_clock_reg32,
++ ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
++ dentry);
++}
++
+ static const struct clk_ops bcm2835_clock_clk_ops = {
+ .is_prepared = bcm2835_clock_is_on,
+ .prepare = bcm2835_clock_on,
+@@ -1404,6 +1503,7 @@ static const struct clk_ops bcm2835_cloc
+ .determine_rate = bcm2835_clock_determine_rate,
+ .set_parent = bcm2835_clock_set_parent,
+ .get_parent = bcm2835_clock_get_parent,
++ .debug_init = bcm2835_clock_debug_init,
+ };
+
+ static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
+@@ -1422,6 +1522,7 @@ static const struct clk_ops bcm2835_vpu_
+ .determine_rate = bcm2835_clock_determine_rate,
+ .set_parent = bcm2835_clock_set_parent,
+ .get_parent = bcm2835_clock_get_parent,
++ .debug_init = bcm2835_clock_debug_init,
+ };
+
+ static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman,
--- /dev/null
+From 63ebb7d70e33861f5f00dd57dcf5e99088d385ab Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 12:51:41 +0000
+Subject: [PATCH 262/304] clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in
+ driver
+
+As the use of BCM2835_CLOCK_COUNT in
+include/dt-bindings/clock/bcm2835.h is frowned upon as
+it needs to get modified every time a new clock gets introduced
+this patch changes the clk-bcm2835 driver to use a different
+scheme for registration of clocks and pll, so that there
+is no more need for BCM2835_CLOCK_COUNT to be defined.
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 56eb3a2ed9726961e1bcfa69d4a3f86d68f0eb52)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 167 ++++++++++++++++++++----------------
+ include/dt-bindings/clock/bcm2835.h | 2 -
+ 2 files changed, 94 insertions(+), 75 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -301,7 +301,7 @@ struct bcm2835_cprman {
+ const char *osc_name;
+
+ struct clk_onecell_data onecell;
+- struct clk *clks[BCM2835_CLOCK_COUNT];
++ struct clk *clks[];
+ };
+
+ static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
+@@ -853,6 +853,25 @@ static const struct bcm2835_clock_data b
+ .is_mash_clock = true,
+ };
+
++struct bcm2835_gate_data {
++ const char *name;
++ const char *parent;
++
++ u32 ctl_reg;
++};
++
++/*
++ * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
++ * you have the debug bit set in the power manager, which we
++ * don't bother exposing) are individual gates off of the
++ * non-stop vpu clock.
++ */
++static const struct bcm2835_gate_data bcm2835_clock_peri_image_data = {
++ .name = "peri_image",
++ .parent = "vpu",
++ .ctl_reg = CM_PERIICTL,
++};
++
+ struct bcm2835_pll {
+ struct clk_hw hw;
+ struct bcm2835_cprman *cprman;
+@@ -1654,14 +1673,81 @@ static struct clk *bcm2835_register_cloc
+ return devm_clk_register(cprman->dev, &clock->hw);
+ }
+
++static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,
++ const struct bcm2835_gate_data *data)
++{
++ return clk_register_gate(cprman->dev, data->name, data->parent,
++ CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
++ cprman->regs + data->ctl_reg,
++ CM_GATE_BIT, 0, &cprman->regs_lock);
++}
++
++typedef struct clk *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
++ const void *data);
++struct bcm2835_clk_desc {
++ bcm2835_clk_register clk_register;
++ const void *data;
++};
++
++#define _REGISTER(f, d) { .clk_register = (bcm2835_clk_register)f, \
++ .data = d }
++#define REGISTER_PLL(d) _REGISTER(&bcm2835_register_pll, d)
++#define REGISTER_PLL_DIV(d) _REGISTER(&bcm2835_register_pll_divider, d)
++#define REGISTER_CLK(d) _REGISTER(&bcm2835_register_clock, d)
++#define REGISTER_GATE(d) _REGISTER(&bcm2835_register_gate, d)
++
++static const struct bcm2835_clk_desc clk_desc_array[] = {
++ /* register PLL */
++ [BCM2835_PLLA] = REGISTER_PLL(&bcm2835_plla_data),
++ [BCM2835_PLLB] = REGISTER_PLL(&bcm2835_pllb_data),
++ [BCM2835_PLLC] = REGISTER_PLL(&bcm2835_pllc_data),
++ [BCM2835_PLLD] = REGISTER_PLL(&bcm2835_plld_data),
++ [BCM2835_PLLH] = REGISTER_PLL(&bcm2835_pllh_data),
++ /* the PLL dividers */
++ [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(&bcm2835_plla_core_data),
++ [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(&bcm2835_plla_per_data),
++ [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(&bcm2835_pllc_core0_data),
++ [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(&bcm2835_pllc_core1_data),
++ [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(&bcm2835_pllc_core2_data),
++ [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(&bcm2835_pllc_per_data),
++ [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(&bcm2835_plld_core_data),
++ [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(&bcm2835_plld_per_data),
++ [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(&bcm2835_pllh_rcal_data),
++ [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(&bcm2835_pllh_aux_data),
++ [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(&bcm2835_pllh_pix_data),
++ /* the clocks */
++ [BCM2835_CLOCK_TIMER] = REGISTER_CLK(&bcm2835_clock_timer_data),
++ [BCM2835_CLOCK_OTP] = REGISTER_CLK(&bcm2835_clock_otp_data),
++ [BCM2835_CLOCK_TSENS] = REGISTER_CLK(&bcm2835_clock_tsens_data),
++ [BCM2835_CLOCK_VPU] = REGISTER_CLK(&bcm2835_clock_vpu_data),
++ [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
++ [BCM2835_CLOCK_ISP] = REGISTER_CLK(&bcm2835_clock_isp_data),
++ [BCM2835_CLOCK_H264] = REGISTER_CLK(&bcm2835_clock_h264_data),
++ [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
++ [BCM2835_CLOCK_SDRAM] = REGISTER_CLK(&bcm2835_clock_sdram_data),
++ [BCM2835_CLOCK_UART] = REGISTER_CLK(&bcm2835_clock_uart_data),
++ [BCM2835_CLOCK_VEC] = REGISTER_CLK(&bcm2835_clock_vec_data),
++ [BCM2835_CLOCK_HSM] = REGISTER_CLK(&bcm2835_clock_hsm_data),
++ [BCM2835_CLOCK_EMMC] = REGISTER_CLK(&bcm2835_clock_emmc_data),
++ [BCM2835_CLOCK_PWM] = REGISTER_CLK(&bcm2835_clock_pwm_data),
++ /* the gates */
++ [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
++ &bcm2835_clock_peri_image_data),
++};
++
+ static int bcm2835_clk_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+ struct clk **clks;
+ struct bcm2835_cprman *cprman;
+ struct resource *res;
++ const struct bcm2835_clk_desc *desc;
++ const size_t asize = ARRAY_SIZE(clk_desc_array);
++ size_t i;
+
+- cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL);
++ cprman = devm_kzalloc(dev,
++ sizeof(*cprman) + asize * sizeof(*clks),
++ GFP_KERNEL);
+ if (!cprman)
+ return -ENOMEM;
+
+@@ -1678,80 +1764,15 @@ static int bcm2835_clk_probe(struct plat
+
+ platform_set_drvdata(pdev, cprman);
+
+- cprman->onecell.clk_num = BCM2835_CLOCK_COUNT;
++ cprman->onecell.clk_num = asize;
+ cprman->onecell.clks = cprman->clks;
+ clks = cprman->clks;
+
+- clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data);
+- clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data);
+- clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data);
+- clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data);
+- clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data);
+-
+- clks[BCM2835_PLLA_CORE] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data);
+- clks[BCM2835_PLLA_PER] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data);
+- clks[BCM2835_PLLC_CORE0] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data);
+- clks[BCM2835_PLLC_CORE1] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data);
+- clks[BCM2835_PLLC_CORE2] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data);
+- clks[BCM2835_PLLC_PER] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data);
+- clks[BCM2835_PLLD_CORE] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data);
+- clks[BCM2835_PLLD_PER] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data);
+- clks[BCM2835_PLLH_RCAL] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data);
+- clks[BCM2835_PLLH_AUX] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data);
+- clks[BCM2835_PLLH_PIX] =
+- bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data);
+-
+- clks[BCM2835_CLOCK_TIMER] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_timer_data);
+- clks[BCM2835_CLOCK_OTP] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_otp_data);
+- clks[BCM2835_CLOCK_TSENS] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data);
+- clks[BCM2835_CLOCK_VPU] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data);
+- clks[BCM2835_CLOCK_V3D] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
+- clks[BCM2835_CLOCK_ISP] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_isp_data);
+- clks[BCM2835_CLOCK_H264] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_h264_data);
+- clks[BCM2835_CLOCK_V3D] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
+- clks[BCM2835_CLOCK_SDRAM] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data);
+- clks[BCM2835_CLOCK_UART] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_uart_data);
+- clks[BCM2835_CLOCK_VEC] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_vec_data);
+- clks[BCM2835_CLOCK_HSM] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data);
+- clks[BCM2835_CLOCK_EMMC] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data);
+-
+- /*
+- * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
+- * you have the debug bit set in the power manager, which we
+- * don't bother exposing) are individual gates off of the
+- * non-stop vpu clock.
+- */
+- clks[BCM2835_CLOCK_PERI_IMAGE] =
+- clk_register_gate(dev, "peri_image", "vpu",
+- CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
+- cprman->regs + CM_PERIICTL, CM_GATE_BIT,
+- 0, &cprman->regs_lock);
+-
+- clks[BCM2835_CLOCK_PWM] =
+- bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
++ for (i = 0; i < asize; i++) {
++ desc = &clk_desc_array[i];
++ if (desc->clk_register && desc->data)
++ clks[i] = desc->clk_register(cprman, desc->data);
++ }
+
+ return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
+ &cprman->onecell);
+--- a/include/dt-bindings/clock/bcm2835.h
++++ b/include/dt-bindings/clock/bcm2835.h
+@@ -44,5 +44,3 @@
+ #define BCM2835_CLOCK_EMMC 28
+ #define BCM2835_CLOCK_PERI_IMAGE 29
+ #define BCM2835_CLOCK_PWM 30
+-
+-#define BCM2835_CLOCK_COUNT 31
--- /dev/null
+From 760cf54c7a5a8627555a9adbf96e8aae0fcfd790 Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 12:51:42 +0000
+Subject: [PATCH 263/304] clk: bcm2835: reorganize bcm2835_clock_array
+ assignment
+
+Reorganize bcm2835_clock_array so that there is no more
+need for separate bcm2835_*_data structures to be defined.
+Instead the required structures are generated inline via
+helper macros.
+
+To allow this to also work for pll alone it was required that
+the parent_pll was changed from a pointer to bcm2835_pll_data
+to the name of the pll instead.
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 3b15afefbef9b5952e3d68ad73d93f981b9faca8)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 852 +++++++++++++++++++-----------------------
+ 1 file changed, 393 insertions(+), 459 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -418,115 +418,10 @@ static const struct bcm2835_pll_ana_bits
+ .fb_prediv_mask = BIT(11),
+ };
+
+-/*
+- * PLLA is the auxiliary PLL, used to drive the CCP2 (Compact Camera
+- * Port 2) transmitter clock.
+- *
+- * It is in the PX LDO power domain, which is on when the AUDIO domain
+- * is on.
+- */
+-static const struct bcm2835_pll_data bcm2835_plla_data = {
+- .name = "plla",
+- .cm_ctrl_reg = CM_PLLA,
+- .a2w_ctrl_reg = A2W_PLLA_CTRL,
+- .frac_reg = A2W_PLLA_FRAC,
+- .ana_reg_base = A2W_PLLA_ANA0,
+- .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
+- .lock_mask = CM_LOCK_FLOCKA,
+-
+- .ana = &bcm2835_ana_default,
+-
+- .min_rate = 600000000u,
+- .max_rate = 2400000000u,
+- .max_fb_rate = BCM2835_MAX_FB_RATE,
+-};
+-
+-/* PLLB is used for the ARM's clock. */
+-static const struct bcm2835_pll_data bcm2835_pllb_data = {
+- .name = "pllb",
+- .cm_ctrl_reg = CM_PLLB,
+- .a2w_ctrl_reg = A2W_PLLB_CTRL,
+- .frac_reg = A2W_PLLB_FRAC,
+- .ana_reg_base = A2W_PLLB_ANA0,
+- .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
+- .lock_mask = CM_LOCK_FLOCKB,
+-
+- .ana = &bcm2835_ana_default,
+-
+- .min_rate = 600000000u,
+- .max_rate = 3000000000u,
+- .max_fb_rate = BCM2835_MAX_FB_RATE,
+-};
+-
+-/*
+- * PLLC is the core PLL, used to drive the core VPU clock.
+- *
+- * It is in the PX LDO power domain, which is on when the AUDIO domain
+- * is on.
+-*/
+-static const struct bcm2835_pll_data bcm2835_pllc_data = {
+- .name = "pllc",
+- .cm_ctrl_reg = CM_PLLC,
+- .a2w_ctrl_reg = A2W_PLLC_CTRL,
+- .frac_reg = A2W_PLLC_FRAC,
+- .ana_reg_base = A2W_PLLC_ANA0,
+- .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
+- .lock_mask = CM_LOCK_FLOCKC,
+-
+- .ana = &bcm2835_ana_default,
+-
+- .min_rate = 600000000u,
+- .max_rate = 3000000000u,
+- .max_fb_rate = BCM2835_MAX_FB_RATE,
+-};
+-
+-/*
+- * PLLD is the display PLL, used to drive DSI display panels.
+- *
+- * It is in the PX LDO power domain, which is on when the AUDIO domain
+- * is on.
+- */
+-static const struct bcm2835_pll_data bcm2835_plld_data = {
+- .name = "plld",
+- .cm_ctrl_reg = CM_PLLD,
+- .a2w_ctrl_reg = A2W_PLLD_CTRL,
+- .frac_reg = A2W_PLLD_FRAC,
+- .ana_reg_base = A2W_PLLD_ANA0,
+- .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
+- .lock_mask = CM_LOCK_FLOCKD,
+-
+- .ana = &bcm2835_ana_default,
+-
+- .min_rate = 600000000u,
+- .max_rate = 2400000000u,
+- .max_fb_rate = BCM2835_MAX_FB_RATE,
+-};
+-
+-/*
+- * PLLH is used to supply the pixel clock or the AUX clock for the TV
+- * encoder.
+- *
+- * It is in the HDMI power domain.
+- */
+-static const struct bcm2835_pll_data bcm2835_pllh_data = {
+- "pllh",
+- .cm_ctrl_reg = CM_PLLH,
+- .a2w_ctrl_reg = A2W_PLLH_CTRL,
+- .frac_reg = A2W_PLLH_FRAC,
+- .ana_reg_base = A2W_PLLH_ANA0,
+- .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
+- .lock_mask = CM_LOCK_FLOCKH,
+-
+- .ana = &bcm2835_ana_pllh,
+-
+- .min_rate = 600000000u,
+- .max_rate = 3000000000u,
+- .max_fb_rate = BCM2835_MAX_FB_RATE,
+-};
+-
+ struct bcm2835_pll_divider_data {
+ const char *name;
+- const struct bcm2835_pll_data *source_pll;
++ const char *source_pll;
++
+ u32 cm_reg;
+ u32 a2w_reg;
+
+@@ -535,124 +430,6 @@ struct bcm2835_pll_divider_data {
+ u32 fixed_divider;
+ };
+
+-static const struct bcm2835_pll_divider_data bcm2835_plla_core_data = {
+- .name = "plla_core",
+- .source_pll = &bcm2835_plla_data,
+- .cm_reg = CM_PLLA,
+- .a2w_reg = A2W_PLLA_CORE,
+- .load_mask = CM_PLLA_LOADCORE,
+- .hold_mask = CM_PLLA_HOLDCORE,
+- .fixed_divider = 1,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_plla_per_data = {
+- .name = "plla_per",
+- .source_pll = &bcm2835_plla_data,
+- .cm_reg = CM_PLLA,
+- .a2w_reg = A2W_PLLA_PER,
+- .load_mask = CM_PLLA_LOADPER,
+- .hold_mask = CM_PLLA_HOLDPER,
+- .fixed_divider = 1,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_pllb_arm_data = {
+- .name = "pllb_arm",
+- .source_pll = &bcm2835_pllb_data,
+- .cm_reg = CM_PLLB,
+- .a2w_reg = A2W_PLLB_ARM,
+- .load_mask = CM_PLLB_LOADARM,
+- .hold_mask = CM_PLLB_HOLDARM,
+- .fixed_divider = 1,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_pllc_core0_data = {
+- .name = "pllc_core0",
+- .source_pll = &bcm2835_pllc_data,
+- .cm_reg = CM_PLLC,
+- .a2w_reg = A2W_PLLC_CORE0,
+- .load_mask = CM_PLLC_LOADCORE0,
+- .hold_mask = CM_PLLC_HOLDCORE0,
+- .fixed_divider = 1,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_pllc_core1_data = {
+- .name = "pllc_core1", .source_pll = &bcm2835_pllc_data,
+- .cm_reg = CM_PLLC, A2W_PLLC_CORE1,
+- .load_mask = CM_PLLC_LOADCORE1,
+- .hold_mask = CM_PLLC_HOLDCORE1,
+- .fixed_divider = 1,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_pllc_core2_data = {
+- .name = "pllc_core2",
+- .source_pll = &bcm2835_pllc_data,
+- .cm_reg = CM_PLLC,
+- .a2w_reg = A2W_PLLC_CORE2,
+- .load_mask = CM_PLLC_LOADCORE2,
+- .hold_mask = CM_PLLC_HOLDCORE2,
+- .fixed_divider = 1,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_pllc_per_data = {
+- .name = "pllc_per",
+- .source_pll = &bcm2835_pllc_data,
+- .cm_reg = CM_PLLC,
+- .a2w_reg = A2W_PLLC_PER,
+- .load_mask = CM_PLLC_LOADPER,
+- .hold_mask = CM_PLLC_HOLDPER,
+- .fixed_divider = 1,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_plld_core_data = {
+- .name = "plld_core",
+- .source_pll = &bcm2835_plld_data,
+- .cm_reg = CM_PLLD,
+- .a2w_reg = A2W_PLLD_CORE,
+- .load_mask = CM_PLLD_LOADCORE,
+- .hold_mask = CM_PLLD_HOLDCORE,
+- .fixed_divider = 1,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_plld_per_data = {
+- .name = "plld_per",
+- .source_pll = &bcm2835_plld_data,
+- .cm_reg = CM_PLLD,
+- .a2w_reg = A2W_PLLD_PER,
+- .load_mask = CM_PLLD_LOADPER,
+- .hold_mask = CM_PLLD_HOLDPER,
+- .fixed_divider = 1,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_pllh_rcal_data = {
+- .name = "pllh_rcal",
+- .source_pll = &bcm2835_pllh_data,
+- .cm_reg = CM_PLLH,
+- .a2w_reg = A2W_PLLH_RCAL,
+- .load_mask = CM_PLLH_LOADRCAL,
+- .hold_mask = 0,
+- .fixed_divider = 10,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_pllh_aux_data = {
+- .name = "pllh_aux",
+- .source_pll = &bcm2835_pllh_data,
+- .cm_reg = CM_PLLH,
+- .a2w_reg = A2W_PLLH_AUX,
+- .load_mask = CM_PLLH_LOADAUX,
+- .hold_mask = 0,
+- .fixed_divider = 10,
+-};
+-
+-static const struct bcm2835_pll_divider_data bcm2835_pllh_pix_data = {
+- .name = "pllh_pix",
+- .source_pll = &bcm2835_pllh_data,
+- .cm_reg = CM_PLLH,
+- .a2w_reg = A2W_PLLH_PIX,
+- .load_mask = CM_PLLH_LOADPIX,
+- .hold_mask = 0,
+- .fixed_divider = 10,
+-};
+-
+ struct bcm2835_clock_data {
+ const char *name;
+
+@@ -671,188 +448,6 @@ struct bcm2835_clock_data {
+ bool is_mash_clock;
+ };
+
+-static const char *const bcm2835_clock_per_parents[] = {
+- "gnd",
+- "xosc",
+- "testdebug0",
+- "testdebug1",
+- "plla_per",
+- "pllc_per",
+- "plld_per",
+- "pllh_aux",
+-};
+-
+-static const char *const bcm2835_clock_vpu_parents[] = {
+- "gnd",
+- "xosc",
+- "testdebug0",
+- "testdebug1",
+- "plla_core",
+- "pllc_core0",
+- "plld_core",
+- "pllh_aux",
+- "pllc_core1",
+- "pllc_core2",
+-};
+-
+-static const char *const bcm2835_clock_osc_parents[] = {
+- "gnd",
+- "xosc",
+- "testdebug0",
+- "testdebug1"
+-};
+-
+-/*
+- * Used for a 1Mhz clock for the system clocksource, and also used by
+- * the watchdog timer and the camera pulse generator.
+- */
+-static const struct bcm2835_clock_data bcm2835_clock_timer_data = {
+- .name = "timer",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
+- .parents = bcm2835_clock_osc_parents,
+- .ctl_reg = CM_TIMERCTL,
+- .div_reg = CM_TIMERDIV,
+- .int_bits = 6,
+- .frac_bits = 12,
+-};
+-
+-/* One Time Programmable Memory clock. Maximum 10Mhz. */
+-static const struct bcm2835_clock_data bcm2835_clock_otp_data = {
+- .name = "otp",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
+- .parents = bcm2835_clock_osc_parents,
+- .ctl_reg = CM_OTPCTL,
+- .div_reg = CM_OTPDIV,
+- .int_bits = 4,
+- .frac_bits = 0,
+-};
+-
+-/*
+- * VPU clock. This doesn't have an enable bit, since it drives the
+- * bus for everything else, and is special so it doesn't need to be
+- * gated for rate changes. It is also known as "clk_audio" in various
+- * hardware documentation.
+- */
+-static const struct bcm2835_clock_data bcm2835_clock_vpu_data = {
+- .name = "vpu",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
+- .parents = bcm2835_clock_vpu_parents,
+- .ctl_reg = CM_VPUCTL,
+- .div_reg = CM_VPUDIV,
+- .int_bits = 12,
+- .frac_bits = 8,
+- .is_vpu_clock = true,
+-};
+-
+-static const struct bcm2835_clock_data bcm2835_clock_v3d_data = {
+- .name = "v3d",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
+- .parents = bcm2835_clock_vpu_parents,
+- .ctl_reg = CM_V3DCTL,
+- .div_reg = CM_V3DDIV,
+- .int_bits = 4,
+- .frac_bits = 8,
+-};
+-
+-static const struct bcm2835_clock_data bcm2835_clock_isp_data = {
+- .name = "isp",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
+- .parents = bcm2835_clock_vpu_parents,
+- .ctl_reg = CM_ISPCTL,
+- .div_reg = CM_ISPDIV,
+- .int_bits = 4,
+- .frac_bits = 8,
+-};
+-
+-static const struct bcm2835_clock_data bcm2835_clock_h264_data = {
+- .name = "h264",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
+- .parents = bcm2835_clock_vpu_parents,
+- .ctl_reg = CM_H264CTL,
+- .div_reg = CM_H264DIV,
+- .int_bits = 4,
+- .frac_bits = 8,
+-};
+-
+-/* TV encoder clock. Only operating frequency is 108Mhz. */
+-static const struct bcm2835_clock_data bcm2835_clock_vec_data = {
+- .name = "vec",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
+- .parents = bcm2835_clock_per_parents,
+- .ctl_reg = CM_VECCTL,
+- .div_reg = CM_VECDIV,
+- .int_bits = 4,
+- .frac_bits = 0,
+-};
+-
+-static const struct bcm2835_clock_data bcm2835_clock_uart_data = {
+- .name = "uart",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
+- .parents = bcm2835_clock_per_parents,
+- .ctl_reg = CM_UARTCTL,
+- .div_reg = CM_UARTDIV,
+- .int_bits = 10,
+- .frac_bits = 12,
+-};
+-
+-/* HDMI state machine */
+-static const struct bcm2835_clock_data bcm2835_clock_hsm_data = {
+- .name = "hsm",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
+- .parents = bcm2835_clock_per_parents,
+- .ctl_reg = CM_HSMCTL,
+- .div_reg = CM_HSMDIV,
+- .int_bits = 4,
+- .frac_bits = 8,
+-};
+-
+-/*
+- * Secondary SDRAM clock. Used for low-voltage modes when the PLL in
+- * the SDRAM controller can't be used.
+- */
+-static const struct bcm2835_clock_data bcm2835_clock_sdram_data = {
+- .name = "sdram",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
+- .parents = bcm2835_clock_vpu_parents,
+- .ctl_reg = CM_SDCCTL,
+- .div_reg = CM_SDCDIV,
+- .int_bits = 6,
+- .frac_bits = 0,
+-};
+-
+-/* Clock for the temperature sensor. Generally run at 2Mhz, max 5Mhz. */
+-static const struct bcm2835_clock_data bcm2835_clock_tsens_data = {
+- .name = "tsens",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
+- .parents = bcm2835_clock_osc_parents,
+- .ctl_reg = CM_TSENSCTL,
+- .div_reg = CM_TSENSDIV,
+- .int_bits = 5,
+- .frac_bits = 0,
+-};
+-
+-/* Arasan EMMC clock */
+-static const struct bcm2835_clock_data bcm2835_clock_emmc_data = {
+- .name = "emmc",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
+- .parents = bcm2835_clock_per_parents,
+- .ctl_reg = CM_EMMCCTL,
+- .div_reg = CM_EMMCDIV,
+- .int_bits = 4,
+- .frac_bits = 8,
+-};
+-
+-static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
+- .name = "pwm",
+- .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
+- .parents = bcm2835_clock_per_parents,
+- .ctl_reg = CM_PWMCTL,
+- .div_reg = CM_PWMDIV,
+- .int_bits = 12,
+- .frac_bits = 12,
+- .is_mash_clock = true,
+-};
+-
+ struct bcm2835_gate_data {
+ const char *name;
+ const char *parent;
+@@ -860,18 +455,6 @@ struct bcm2835_gate_data {
+ u32 ctl_reg;
+ };
+
+-/*
+- * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
+- * you have the debug bit set in the power manager, which we
+- * don't bother exposing) are individual gates off of the
+- * non-stop vpu clock.
+- */
+-static const struct bcm2835_gate_data bcm2835_clock_peri_image_data = {
+- .name = "peri_image",
+- .parent = "vpu",
+- .ctl_reg = CM_PERIICTL,
+-};
+-
+ struct bcm2835_pll {
+ struct clk_hw hw;
+ struct bcm2835_cprman *cprman;
+@@ -1590,7 +1173,7 @@ bcm2835_register_pll_divider(struct bcm2
+
+ memset(&init, 0, sizeof(init));
+
+- init.parent_names = &data->source_pll->name;
++ init.parent_names = &data->source_pll;
+ init.num_parents = 1;
+ init.name = divider_name;
+ init.ops = &bcm2835_pll_divider_clk_ops;
+@@ -1689,50 +1272,401 @@ struct bcm2835_clk_desc {
+ const void *data;
+ };
+
+-#define _REGISTER(f, d) { .clk_register = (bcm2835_clk_register)f, \
+- .data = d }
+-#define REGISTER_PLL(d) _REGISTER(&bcm2835_register_pll, d)
+-#define REGISTER_PLL_DIV(d) _REGISTER(&bcm2835_register_pll_divider, d)
+-#define REGISTER_CLK(d) _REGISTER(&bcm2835_register_clock, d)
+-#define REGISTER_GATE(d) _REGISTER(&bcm2835_register_gate, d)
++/* assignment helper macros for different clock types */
++#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
++ .data = __VA_ARGS__ }
++#define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
++ &(struct bcm2835_pll_data) \
++ {__VA_ARGS__})
++#define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
++ &(struct bcm2835_pll_divider_data) \
++ {__VA_ARGS__})
++#define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
++ &(struct bcm2835_clock_data) \
++ {__VA_ARGS__})
++#define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
++ &(struct bcm2835_gate_data) \
++ {__VA_ARGS__})
++
++/* parent mux arrays plus helper macros */
++
++/* main oscillator parent mux */
++static const char *const bcm2835_clock_osc_parents[] = {
++ "gnd",
++ "xosc",
++ "testdebug0",
++ "testdebug1"
++};
++
++#define REGISTER_OSC_CLK(...) REGISTER_CLK( \
++ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
++ .parents = bcm2835_clock_osc_parents, \
++ __VA_ARGS__)
++
++/* main peripherial parent mux */
++static const char *const bcm2835_clock_per_parents[] = {
++ "gnd",
++ "xosc",
++ "testdebug0",
++ "testdebug1",
++ "plla_per",
++ "pllc_per",
++ "plld_per",
++ "pllh_aux",
++};
++
++#define REGISTER_PER_CLK(...) REGISTER_CLK( \
++ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
++ .parents = bcm2835_clock_per_parents, \
++ __VA_ARGS__)
++
++/* main vpu parent mux */
++static const char *const bcm2835_clock_vpu_parents[] = {
++ "gnd",
++ "xosc",
++ "testdebug0",
++ "testdebug1",
++ "plla_core",
++ "pllc_core0",
++ "plld_core",
++ "pllh_aux",
++ "pllc_core1",
++ "pllc_core2",
++};
++
++#define REGISTER_VPU_CLK(...) REGISTER_CLK( \
++ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
++ .parents = bcm2835_clock_vpu_parents, \
++ __VA_ARGS__)
+
++/*
++ * the real definition of all the pll, pll_dividers and clocks
++ * these make use of the above REGISTER_* macros
++ */
+ static const struct bcm2835_clk_desc clk_desc_array[] = {
+- /* register PLL */
+- [BCM2835_PLLA] = REGISTER_PLL(&bcm2835_plla_data),
+- [BCM2835_PLLB] = REGISTER_PLL(&bcm2835_pllb_data),
+- [BCM2835_PLLC] = REGISTER_PLL(&bcm2835_pllc_data),
+- [BCM2835_PLLD] = REGISTER_PLL(&bcm2835_plld_data),
+- [BCM2835_PLLH] = REGISTER_PLL(&bcm2835_pllh_data),
+- /* the PLL dividers */
+- [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(&bcm2835_plla_core_data),
+- [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(&bcm2835_plla_per_data),
+- [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(&bcm2835_pllc_core0_data),
+- [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(&bcm2835_pllc_core1_data),
+- [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(&bcm2835_pllc_core2_data),
+- [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(&bcm2835_pllc_per_data),
+- [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(&bcm2835_plld_core_data),
+- [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(&bcm2835_plld_per_data),
+- [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(&bcm2835_pllh_rcal_data),
+- [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(&bcm2835_pllh_aux_data),
+- [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(&bcm2835_pllh_pix_data),
++ /* the PLL + PLL dividers */
++
++ /*
++ * PLLA is the auxiliary PLL, used to drive the CCP2
++ * (Compact Camera Port 2) transmitter clock.
++ *
++ * It is in the PX LDO power domain, which is on when the
++ * AUDIO domain is on.
++ */
++ [BCM2835_PLLA] = REGISTER_PLL(
++ .name = "plla",
++ .cm_ctrl_reg = CM_PLLA,
++ .a2w_ctrl_reg = A2W_PLLA_CTRL,
++ .frac_reg = A2W_PLLA_FRAC,
++ .ana_reg_base = A2W_PLLA_ANA0,
++ .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
++ .lock_mask = CM_LOCK_FLOCKA,
++
++ .ana = &bcm2835_ana_default,
++
++ .min_rate = 600000000u,
++ .max_rate = 2400000000u,
++ .max_fb_rate = BCM2835_MAX_FB_RATE),
++ [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
++ .name = "plla_core",
++ .source_pll = "plla",
++ .cm_reg = CM_PLLA,
++ .a2w_reg = A2W_PLLA_CORE,
++ .load_mask = CM_PLLA_LOADCORE,
++ .hold_mask = CM_PLLA_HOLDCORE,
++ .fixed_divider = 1),
++ [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
++ .name = "plla_per",
++ .source_pll = "plla",
++ .cm_reg = CM_PLLA,
++ .a2w_reg = A2W_PLLA_PER,
++ .load_mask = CM_PLLA_LOADPER,
++ .hold_mask = CM_PLLA_HOLDPER,
++ .fixed_divider = 1),
++
++ /* PLLB is used for the ARM's clock. */
++ [BCM2835_PLLB] = REGISTER_PLL(
++ .name = "pllb",
++ .cm_ctrl_reg = CM_PLLB,
++ .a2w_ctrl_reg = A2W_PLLB_CTRL,
++ .frac_reg = A2W_PLLB_FRAC,
++ .ana_reg_base = A2W_PLLB_ANA0,
++ .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
++ .lock_mask = CM_LOCK_FLOCKB,
++
++ .ana = &bcm2835_ana_default,
++
++ .min_rate = 600000000u,
++ .max_rate = 3000000000u,
++ .max_fb_rate = BCM2835_MAX_FB_RATE),
++ [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
++ .name = "pllb_arm",
++ .source_pll = "pllb",
++ .cm_reg = CM_PLLB,
++ .a2w_reg = A2W_PLLB_ARM,
++ .load_mask = CM_PLLB_LOADARM,
++ .hold_mask = CM_PLLB_HOLDARM,
++ .fixed_divider = 1),
++
++ /*
++ * PLLC is the core PLL, used to drive the core VPU clock.
++ *
++ * It is in the PX LDO power domain, which is on when the
++ * AUDIO domain is on.
++ */
++ [BCM2835_PLLC] = REGISTER_PLL(
++ .name = "pllc",
++ .cm_ctrl_reg = CM_PLLC,
++ .a2w_ctrl_reg = A2W_PLLC_CTRL,
++ .frac_reg = A2W_PLLC_FRAC,
++ .ana_reg_base = A2W_PLLC_ANA0,
++ .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
++ .lock_mask = CM_LOCK_FLOCKC,
++
++ .ana = &bcm2835_ana_default,
++
++ .min_rate = 600000000u,
++ .max_rate = 3000000000u,
++ .max_fb_rate = BCM2835_MAX_FB_RATE),
++ [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
++ .name = "pllc_core0",
++ .source_pll = "pllc",
++ .cm_reg = CM_PLLC,
++ .a2w_reg = A2W_PLLC_CORE0,
++ .load_mask = CM_PLLC_LOADCORE0,
++ .hold_mask = CM_PLLC_HOLDCORE0,
++ .fixed_divider = 1),
++ [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
++ .name = "pllc_core1",
++ .source_pll = "pllc",
++ .cm_reg = CM_PLLC,
++ .a2w_reg = A2W_PLLC_CORE1,
++ .load_mask = CM_PLLC_LOADCORE1,
++ .hold_mask = CM_PLLC_HOLDCORE1,
++ .fixed_divider = 1),
++ [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
++ .name = "pllc_core2",
++ .source_pll = "pllc",
++ .cm_reg = CM_PLLC,
++ .a2w_reg = A2W_PLLC_CORE2,
++ .load_mask = CM_PLLC_LOADCORE2,
++ .hold_mask = CM_PLLC_HOLDCORE2,
++ .fixed_divider = 1),
++ [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
++ .name = "pllc_per",
++ .source_pll = "pllc",
++ .cm_reg = CM_PLLC,
++ .a2w_reg = A2W_PLLC_PER,
++ .load_mask = CM_PLLC_LOADPER,
++ .hold_mask = CM_PLLC_HOLDPER,
++ .fixed_divider = 1),
++
++ /*
++ * PLLD is the display PLL, used to drive DSI display panels.
++ *
++ * It is in the PX LDO power domain, which is on when the
++ * AUDIO domain is on.
++ */
++ [BCM2835_PLLD] = REGISTER_PLL(
++ .name = "plld",
++ .cm_ctrl_reg = CM_PLLD,
++ .a2w_ctrl_reg = A2W_PLLD_CTRL,
++ .frac_reg = A2W_PLLD_FRAC,
++ .ana_reg_base = A2W_PLLD_ANA0,
++ .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
++ .lock_mask = CM_LOCK_FLOCKD,
++
++ .ana = &bcm2835_ana_default,
++
++ .min_rate = 600000000u,
++ .max_rate = 2400000000u,
++ .max_fb_rate = BCM2835_MAX_FB_RATE),
++ [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
++ .name = "plld_core",
++ .source_pll = "plld",
++ .cm_reg = CM_PLLD,
++ .a2w_reg = A2W_PLLD_CORE,
++ .load_mask = CM_PLLD_LOADCORE,
++ .hold_mask = CM_PLLD_HOLDCORE,
++ .fixed_divider = 1),
++ [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
++ .name = "plld_per",
++ .source_pll = "plld",
++ .cm_reg = CM_PLLD,
++ .a2w_reg = A2W_PLLD_PER,
++ .load_mask = CM_PLLD_LOADPER,
++ .hold_mask = CM_PLLD_HOLDPER,
++ .fixed_divider = 1),
++
++ /*
++ * PLLH is used to supply the pixel clock or the AUX clock for the
++ * TV encoder.
++ *
++ * It is in the HDMI power domain.
++ */
++ [BCM2835_PLLH] = REGISTER_PLL(
++ "pllh",
++ .cm_ctrl_reg = CM_PLLH,
++ .a2w_ctrl_reg = A2W_PLLH_CTRL,
++ .frac_reg = A2W_PLLH_FRAC,
++ .ana_reg_base = A2W_PLLH_ANA0,
++ .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
++ .lock_mask = CM_LOCK_FLOCKH,
++
++ .ana = &bcm2835_ana_pllh,
++
++ .min_rate = 600000000u,
++ .max_rate = 3000000000u,
++ .max_fb_rate = BCM2835_MAX_FB_RATE),
++ [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
++ .name = "pllh_rcal",
++ .source_pll = "pllh",
++ .cm_reg = CM_PLLH,
++ .a2w_reg = A2W_PLLH_RCAL,
++ .load_mask = CM_PLLH_LOADRCAL,
++ .hold_mask = 0,
++ .fixed_divider = 10),
++ [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
++ .name = "pllh_aux",
++ .source_pll = "pllh",
++ .cm_reg = CM_PLLH,
++ .a2w_reg = A2W_PLLH_AUX,
++ .load_mask = CM_PLLH_LOADAUX,
++ .hold_mask = 0,
++ .fixed_divider = 10),
++ [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
++ .name = "pllh_pix",
++ .source_pll = "pllh",
++ .cm_reg = CM_PLLH,
++ .a2w_reg = A2W_PLLH_PIX,
++ .load_mask = CM_PLLH_LOADPIX,
++ .hold_mask = 0,
++ .fixed_divider = 10),
++
+ /* the clocks */
+- [BCM2835_CLOCK_TIMER] = REGISTER_CLK(&bcm2835_clock_timer_data),
+- [BCM2835_CLOCK_OTP] = REGISTER_CLK(&bcm2835_clock_otp_data),
+- [BCM2835_CLOCK_TSENS] = REGISTER_CLK(&bcm2835_clock_tsens_data),
+- [BCM2835_CLOCK_VPU] = REGISTER_CLK(&bcm2835_clock_vpu_data),
+- [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
+- [BCM2835_CLOCK_ISP] = REGISTER_CLK(&bcm2835_clock_isp_data),
+- [BCM2835_CLOCK_H264] = REGISTER_CLK(&bcm2835_clock_h264_data),
+- [BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
+- [BCM2835_CLOCK_SDRAM] = REGISTER_CLK(&bcm2835_clock_sdram_data),
+- [BCM2835_CLOCK_UART] = REGISTER_CLK(&bcm2835_clock_uart_data),
+- [BCM2835_CLOCK_VEC] = REGISTER_CLK(&bcm2835_clock_vec_data),
+- [BCM2835_CLOCK_HSM] = REGISTER_CLK(&bcm2835_clock_hsm_data),
+- [BCM2835_CLOCK_EMMC] = REGISTER_CLK(&bcm2835_clock_emmc_data),
+- [BCM2835_CLOCK_PWM] = REGISTER_CLK(&bcm2835_clock_pwm_data),
++
++ /* clocks with oscillator parent mux */
++
++ /* One Time Programmable Memory clock. Maximum 10Mhz. */
++ [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
++ .name = "otp",
++ .ctl_reg = CM_OTPCTL,
++ .div_reg = CM_OTPDIV,
++ .int_bits = 4,
++ .frac_bits = 0),
++ /*
++ * Used for a 1Mhz clock for the system clocksource, and also used
++ * bythe watchdog timer and the camera pulse generator.
++ */
++ [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
++ .name = "timer",
++ .ctl_reg = CM_TIMERCTL,
++ .div_reg = CM_TIMERDIV,
++ .int_bits = 6,
++ .frac_bits = 12),
++ /*
++ * Clock for the temperature sensor.
++ * Generally run at 2Mhz, max 5Mhz.
++ */
++ [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
++ .name = "tsens",
++ .ctl_reg = CM_TSENSCTL,
++ .div_reg = CM_TSENSDIV,
++ .int_bits = 5,
++ .frac_bits = 0),
++
++ /* clocks with vpu parent mux */
++ [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
++ .name = "h264",
++ .ctl_reg = CM_H264CTL,
++ .div_reg = CM_H264DIV,
++ .int_bits = 4,
++ .frac_bits = 8),
++ [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
++ .name = "isp",
++ .ctl_reg = CM_ISPCTL,
++ .div_reg = CM_ISPDIV,
++ .int_bits = 4,
++ .frac_bits = 8),
++ /*
++ * Secondary SDRAM clock. Used for low-voltage modes when the PLL
++ * in the SDRAM controller can't be used.
++ */
++ [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
++ .name = "sdram",
++ .ctl_reg = CM_SDCCTL,
++ .div_reg = CM_SDCDIV,
++ .int_bits = 6,
++ .frac_bits = 0),
++ [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
++ .name = "v3d",
++ .ctl_reg = CM_V3DCTL,
++ .div_reg = CM_V3DDIV,
++ .int_bits = 4,
++ .frac_bits = 8),
++ /*
++ * VPU clock. This doesn't have an enable bit, since it drives
++ * the bus for everything else, and is special so it doesn't need
++ * to be gated for rate changes. It is also known as "clk_audio"
++ * in various hardware documentation.
++ */
++ [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
++ .name = "vpu",
++ .ctl_reg = CM_VPUCTL,
++ .div_reg = CM_VPUDIV,
++ .int_bits = 12,
++ .frac_bits = 8,
++ .is_vpu_clock = true),
++
++ /* clocks with per parent mux */
++
++ /* Arasan EMMC clock */
++ [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
++ .name = "emmc",
++ .ctl_reg = CM_EMMCCTL,
++ .div_reg = CM_EMMCDIV,
++ .int_bits = 4,
++ .frac_bits = 8),
++ /* HDMI state machine */
++ [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
++ .name = "hsm",
++ .ctl_reg = CM_HSMCTL,
++ .div_reg = CM_HSMDIV,
++ .int_bits = 4,
++ .frac_bits = 8),
++ [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
++ .name = "pwm",
++ .ctl_reg = CM_PWMCTL,
++ .div_reg = CM_PWMDIV,
++ .int_bits = 12,
++ .frac_bits = 12,
++ .is_mash_clock = true),
++ [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
++ .name = "uart",
++ .ctl_reg = CM_UARTCTL,
++ .div_reg = CM_UARTDIV,
++ .int_bits = 10,
++ .frac_bits = 12),
++ /* TV encoder clock. Only operating frequency is 108Mhz. */
++ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
++ .name = "vec",
++ .ctl_reg = CM_VECCTL,
++ .div_reg = CM_VECDIV,
++ .int_bits = 4,
++ .frac_bits = 0),
++
+ /* the gates */
++
++ /*
++ * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
++ * you have the debug bit set in the power manager, which we
++ * don't bother exposing) are individual gates off of the
++ * non-stop vpu clock.
++ */
+ [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
+- &bcm2835_clock_peri_image_data),
++ .name = "peri_image",
++ .parent = "vpu",
++ .ctl_reg = CM_PERIICTL),
+ };
+
+ static int bcm2835_clk_probe(struct platform_device *pdev)
--- /dev/null
+From 53b35c410aed20a1bfce25d4bdec7bb1449292ec Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 12:51:43 +0000
+Subject: [PATCH 264/304] clk: bcm2835: enable management of PCM clock
+
+Enable the PCM clock in the SOC, which is used by the
+bcm2835-i2s driver.
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 33b689600f43094a9316a1b582f2286d17bc737b)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 7 +++++++
+ include/dt-bindings/clock/bcm2835.h | 1 +
+ 2 files changed, 8 insertions(+)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1634,6 +1634,13 @@ static const struct bcm2835_clk_desc clk
+ .div_reg = CM_HSMDIV,
+ .int_bits = 4,
+ .frac_bits = 8),
++ [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK(
++ .name = "pcm",
++ .ctl_reg = CM_PCMCTL,
++ .div_reg = CM_PCMDIV,
++ .int_bits = 12,
++ .frac_bits = 12,
++ .is_mash_clock = true),
+ [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
+ .name = "pwm",
+ .ctl_reg = CM_PWMCTL,
+--- a/include/dt-bindings/clock/bcm2835.h
++++ b/include/dt-bindings/clock/bcm2835.h
+@@ -44,3 +44,4 @@
+ #define BCM2835_CLOCK_EMMC 28
+ #define BCM2835_CLOCK_PERI_IMAGE 29
+ #define BCM2835_CLOCK_PWM 30
++#define BCM2835_CLOCK_PCM 31
--- /dev/null
+From 4f420c264a38a1eaec12a52f99f3b315133bca69 Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 15:43:56 +0000
+Subject: [PATCH 265/304] clk: bcm2835: add missing PLL clock dividers
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 728436956aa172b24a3212295f8b53feb6479f32)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 32 ++++++++++++++++++++++++++++++++
+ include/dt-bindings/clock/bcm2835.h | 5 +++++
+ 2 files changed, 37 insertions(+)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -1383,6 +1383,22 @@ static const struct bcm2835_clk_desc clk
+ .load_mask = CM_PLLA_LOADPER,
+ .hold_mask = CM_PLLA_HOLDPER,
+ .fixed_divider = 1),
++ [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
++ .name = "plla_dsi0",
++ .source_pll = "plla",
++ .cm_reg = CM_PLLA,
++ .a2w_reg = A2W_PLLA_DSI0,
++ .load_mask = CM_PLLA_LOADDSI0,
++ .hold_mask = CM_PLLA_HOLDDSI0,
++ .fixed_divider = 1),
++ [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
++ .name = "plla_ccp2",
++ .source_pll = "plla",
++ .cm_reg = CM_PLLA,
++ .a2w_reg = A2W_PLLA_CCP2,
++ .load_mask = CM_PLLA_LOADCCP2,
++ .hold_mask = CM_PLLA_HOLDCCP2,
++ .fixed_divider = 1),
+
+ /* PLLB is used for the ARM's clock. */
+ [BCM2835_PLLB] = REGISTER_PLL(
+@@ -1497,6 +1513,22 @@ static const struct bcm2835_clk_desc clk
+ .load_mask = CM_PLLD_LOADPER,
+ .hold_mask = CM_PLLD_HOLDPER,
+ .fixed_divider = 1),
++ [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
++ .name = "plld_dsi0",
++ .source_pll = "plld",
++ .cm_reg = CM_PLLD,
++ .a2w_reg = A2W_PLLD_DSI0,
++ .load_mask = CM_PLLD_LOADDSI0,
++ .hold_mask = CM_PLLD_HOLDDSI0,
++ .fixed_divider = 1),
++ [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
++ .name = "plld_dsi1",
++ .source_pll = "plld",
++ .cm_reg = CM_PLLD,
++ .a2w_reg = A2W_PLLD_DSI1,
++ .load_mask = CM_PLLD_LOADDSI1,
++ .hold_mask = CM_PLLD_HOLDDSI1,
++ .fixed_divider = 1),
+
+ /*
+ * PLLH is used to supply the pixel clock or the AUX clock for the
+--- a/include/dt-bindings/clock/bcm2835.h
++++ b/include/dt-bindings/clock/bcm2835.h
+@@ -45,3 +45,8 @@
+ #define BCM2835_CLOCK_PERI_IMAGE 29
+ #define BCM2835_CLOCK_PWM 30
+ #define BCM2835_CLOCK_PCM 31
++
++#define BCM2835_PLLA_DSI0 32
++#define BCM2835_PLLA_CCP2 33
++#define BCM2835_PLLD_DSI0 34
++#define BCM2835_PLLD_DSI1 35
--- /dev/null
+From 104a92cd1a8b6e83fa0b741e0d0cc37928b0f49b Mon Sep 17 00:00:00 2001
+From: Martin Sperl <kernel@martin.sperl.org>
+Date: Mon, 29 Feb 2016 15:43:57 +0000
+Subject: [PATCH 266/304] clk: bcm2835: add missing osc and per clocks
+
+Add AVE0, DFT, GP0, GP1, GP2, SLIM, SMI, TEC, DPI, CAM0, CAM1, DSI0E,
+and DSI1E. PULSE is not added because it has an extra divider.
+
+Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit d3d6f15fd376e3dbba851724057b112558c70b79)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 90 +++++++++++++++++++++++++++++++++++++
+ include/dt-bindings/clock/bcm2835.h | 14 ++++++
+ 2 files changed, 104 insertions(+)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -117,6 +117,8 @@
+ #define CM_SDCCTL 0x1a8
+ #define CM_SDCDIV 0x1ac
+ #define CM_ARMCTL 0x1b0
++#define CM_AVEOCTL 0x1b8
++#define CM_AVEODIV 0x1bc
+ #define CM_EMMCCTL 0x1c0
+ #define CM_EMMCDIV 0x1c4
+
+@@ -1606,6 +1608,12 @@ static const struct bcm2835_clk_desc clk
+ .div_reg = CM_TSENSDIV,
+ .int_bits = 5,
+ .frac_bits = 0),
++ [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
++ .name = "tec",
++ .ctl_reg = CM_TECCTL,
++ .div_reg = CM_TECDIV,
++ .int_bits = 6,
++ .frac_bits = 0),
+
+ /* clocks with vpu parent mux */
+ [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
+@@ -1620,6 +1628,7 @@ static const struct bcm2835_clk_desc clk
+ .div_reg = CM_ISPDIV,
+ .int_bits = 4,
+ .frac_bits = 8),
++
+ /*
+ * Secondary SDRAM clock. Used for low-voltage modes when the PLL
+ * in the SDRAM controller can't be used.
+@@ -1651,6 +1660,36 @@ static const struct bcm2835_clk_desc clk
+ .is_vpu_clock = true),
+
+ /* clocks with per parent mux */
++ [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
++ .name = "aveo",
++ .ctl_reg = CM_AVEOCTL,
++ .div_reg = CM_AVEODIV,
++ .int_bits = 4,
++ .frac_bits = 0),
++ [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
++ .name = "cam0",
++ .ctl_reg = CM_CAM0CTL,
++ .div_reg = CM_CAM0DIV,
++ .int_bits = 4,
++ .frac_bits = 8),
++ [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
++ .name = "cam1",
++ .ctl_reg = CM_CAM1CTL,
++ .div_reg = CM_CAM1DIV,
++ .int_bits = 4,
++ .frac_bits = 8),
++ [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
++ .name = "dft",
++ .ctl_reg = CM_DFTCTL,
++ .div_reg = CM_DFTDIV,
++ .int_bits = 5,
++ .frac_bits = 0),
++ [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
++ .name = "dpi",
++ .ctl_reg = CM_DPICTL,
++ .div_reg = CM_DPIDIV,
++ .int_bits = 4,
++ .frac_bits = 8),
+
+ /* Arasan EMMC clock */
+ [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
+@@ -1659,6 +1698,29 @@ static const struct bcm2835_clk_desc clk
+ .div_reg = CM_EMMCDIV,
+ .int_bits = 4,
+ .frac_bits = 8),
++
++ /* General purpose (GPIO) clocks */
++ [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
++ .name = "gp0",
++ .ctl_reg = CM_GP0CTL,
++ .div_reg = CM_GP0DIV,
++ .int_bits = 12,
++ .frac_bits = 12,
++ .is_mash_clock = true),
++ [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
++ .name = "gp1",
++ .ctl_reg = CM_GP1CTL,
++ .div_reg = CM_GP1DIV,
++ .int_bits = 12,
++ .frac_bits = 12,
++ .is_mash_clock = true),
++ [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
++ .name = "gp2",
++ .ctl_reg = CM_GP2CTL,
++ .div_reg = CM_GP2DIV,
++ .int_bits = 12,
++ .frac_bits = 12),
++
+ /* HDMI state machine */
+ [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
+ .name = "hsm",
+@@ -1680,12 +1742,26 @@ static const struct bcm2835_clk_desc clk
+ .int_bits = 12,
+ .frac_bits = 12,
+ .is_mash_clock = true),
++ [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
++ .name = "slim",
++ .ctl_reg = CM_SLIMCTL,
++ .div_reg = CM_SLIMDIV,
++ .int_bits = 12,
++ .frac_bits = 12,
++ .is_mash_clock = true),
++ [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
++ .name = "smi",
++ .ctl_reg = CM_SMICTL,
++ .div_reg = CM_SMIDIV,
++ .int_bits = 4,
++ .frac_bits = 8),
+ [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
+ .name = "uart",
+ .ctl_reg = CM_UARTCTL,
+ .div_reg = CM_UARTDIV,
+ .int_bits = 10,
+ .frac_bits = 12),
++
+ /* TV encoder clock. Only operating frequency is 108Mhz. */
+ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
+ .name = "vec",
+@@ -1694,6 +1770,20 @@ static const struct bcm2835_clk_desc clk
+ .int_bits = 4,
+ .frac_bits = 0),
+
++ /* dsi clocks */
++ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
++ .name = "dsi0e",
++ .ctl_reg = CM_DSI0ECTL,
++ .div_reg = CM_DSI0EDIV,
++ .int_bits = 4,
++ .frac_bits = 8),
++ [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
++ .name = "dsi1e",
++ .ctl_reg = CM_DSI1ECTL,
++ .div_reg = CM_DSI1EDIV,
++ .int_bits = 4,
++ .frac_bits = 8),
++
+ /* the gates */
+
+ /*
+--- a/include/dt-bindings/clock/bcm2835.h
++++ b/include/dt-bindings/clock/bcm2835.h
+@@ -50,3 +50,17 @@
+ #define BCM2835_PLLA_CCP2 33
+ #define BCM2835_PLLD_DSI0 34
+ #define BCM2835_PLLD_DSI1 35
++
++#define BCM2835_CLOCK_AVEO 36
++#define BCM2835_CLOCK_DFT 37
++#define BCM2835_CLOCK_GP0 38
++#define BCM2835_CLOCK_GP1 39
++#define BCM2835_CLOCK_GP2 40
++#define BCM2835_CLOCK_SLIM 41
++#define BCM2835_CLOCK_SMI 42
++#define BCM2835_CLOCK_TEC 43
++#define BCM2835_CLOCK_DPI 44
++#define BCM2835_CLOCK_CAM0 45
++#define BCM2835_CLOCK_CAM1 46
++#define BCM2835_CLOCK_DSI0E 47
++#define BCM2835_CLOCK_DSI1E 48
--- /dev/null
+From 66350cdbb13029d143f99c97b0953805afe2f175 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Wed, 13 Apr 2016 13:05:03 -0700
+Subject: [PATCH 267/304] clk: bcm2835: Fix PLL poweron
+
+In poweroff, we set the reset bit and the power down bit, but only
+managed to unset the reset bit for poweron. This meant that if HDMI
+did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the
+PLLH (that had been on at boot time) and never recover.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
+Cc: stable@vger.kernel.org
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+(cherry picked from commit d794a7b18350b7538e64248adf639f2cb8da5fb7)
+---
+ drivers/clk/bcm/clk-bcm2835.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/clk/bcm/clk-bcm2835.c
++++ b/drivers/clk/bcm/clk-bcm2835.c
+@@ -557,6 +557,10 @@ static int bcm2835_pll_on(struct clk_hw
+ const struct bcm2835_pll_data *data = pll->data;
+ ktime_t timeout;
+
++ cprman_write(cprman, data->a2w_ctrl_reg,
++ cprman_read(cprman, data->a2w_ctrl_reg) &
++ ~A2W_PLL_CTRL_PWRDN);
++
+ /* Take the PLL out of reset. */
+ cprman_write(cprman, data->cm_ctrl_reg,
+ cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
--- /dev/null
+From 2a4c0b0a28d07eec49c0388c83958d41d1b96a34 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 1 Dec 2015 16:49:12 -0800
+Subject: [PATCH 268/304] ARM: bcm2835: Define two new packets from the latest
+ firmware.
+
+These packets give us direct access to the firmware's power management
+code, as opposed to GET/SET_POWER_STATE packets that only had a couple
+of domains implemented.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Kevin Hilman <khilman@linaro.org>
+(cherry picked from commit 60d56333e869be6ad6926cdba3ba974512b2183b)
+---
+ include/soc/bcm2835/raspberrypi-firmware.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/soc/bcm2835/raspberrypi-firmware.h
++++ b/include/soc/bcm2835/raspberrypi-firmware.h
+@@ -74,11 +74,13 @@ enum rpi_firmware_property_tag {
+ RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014,
+ RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020,
+ RPI_FIRMWARE_GET_CUSTOMER_OTP = 0x00030021,
++ RPI_FIRMWARE_GET_DOMAIN_STATE = 0x00030030,
+ RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001,
+ RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002,
+ RPI_FIRMWARE_SET_VOLTAGE = 0x00038003,
+ RPI_FIRMWARE_SET_TURBO = 0x00038009,
+ RPI_FIRMWARE_SET_CUSTOMER_OTP = 0x00038021,
++ RPI_FIRMWARE_SET_DOMAIN_STATE = 0x00038030,
+ RPI_FIRMWARE_SET_SDHOST_CLOCK = 0x00038042,
+
+ /* Dispmanx TAGS */
--- /dev/null
+From efc94d4ff30bdf042aa90239b0e0948282677622 Mon Sep 17 00:00:00 2001
+From: Alexander Aring <alex.aring@gmail.com>
+Date: Wed, 16 Dec 2015 16:26:47 -0800
+Subject: [PATCH 269/304] ARM: bcm2835: add rpi power domain driver
+
+This patch adds support for several power domains on Raspberry Pi,
+including USB (so it can be enabled even if the bootloader didn't do
+it), and graphics.
+
+This patch is the combined work of Eric Anholt (who wrote USB support
+inside of the Raspberry Pi firmware driver, and wrote the non-USB
+domain support) and Alexander Aring (who separated the original USB
+work out from the firmware driver).
+
+Signed-off-by: Alexander Aring <alex.aring@gmail.com>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Reviewed-by: Kevin Hilman <khilman@linaro.org>
+(cherry picked from commit a09cd356586d33f64cbe64ee4f5c1a7c4a6abee5)
+---
+ drivers/soc/Kconfig | 1 +
+ drivers/soc/Makefile | 1 +
+ drivers/soc/bcm/Kconfig | 9 +
+ drivers/soc/bcm/Makefile | 1 +
+ drivers/soc/bcm/raspberrypi-power.c | 247 ++++++++++++++++++++++++++
+ include/dt-bindings/power/raspberrypi-power.h | 41 +++++
+ 6 files changed, 300 insertions(+)
+ create mode 100644 drivers/soc/bcm/Kconfig
+ create mode 100644 drivers/soc/bcm/Makefile
+ create mode 100644 drivers/soc/bcm/raspberrypi-power.c
+ create mode 100644 include/dt-bindings/power/raspberrypi-power.h
+
+--- a/drivers/soc/Kconfig
++++ b/drivers/soc/Kconfig
+@@ -1,5 +1,6 @@
+ menu "SOC (System On Chip) specific Drivers"
+
++source "drivers/soc/bcm/Kconfig"
+ source "drivers/soc/brcmstb/Kconfig"
+ source "drivers/soc/mediatek/Kconfig"
+ source "drivers/soc/qcom/Kconfig"
+--- a/drivers/soc/Makefile
++++ b/drivers/soc/Makefile
+@@ -2,6 +2,7 @@
+ # Makefile for the Linux Kernel SOC specific device drivers.
+ #
+
++obj-y += bcm/
+ obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/
+ obj-$(CONFIG_MACH_DOVE) += dove/
+ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
+--- /dev/null
++++ b/drivers/soc/bcm/Kconfig
+@@ -0,0 +1,9 @@
++config RASPBERRYPI_POWER
++ bool "Raspberry Pi power domain driver"
++ depends on ARCH_BCM2835 || COMPILE_TEST
++ depends on RASPBERRYPI_FIRMWARE
++ select PM_GENERIC_DOMAINS if PM
++ select PM_GENERIC_DOMAINS_OF if PM
++ help
++ This enables support for the RPi power domains which can be enabled
++ or disabled via the RPi firmware.
+--- /dev/null
++++ b/drivers/soc/bcm/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_RASPBERRYPI_POWER) += raspberrypi-power.o
+--- /dev/null
++++ b/drivers/soc/bcm/raspberrypi-power.c
+@@ -0,0 +1,247 @@
++/* (C) 2015 Pengutronix, Alexander Aring <aar@pengutronix.de>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Authors:
++ * Alexander Aring <aar@pengutronix.de>
++ * Eric Anholt <eric@anholt.net>
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/pm_domain.h>
++#include <dt-bindings/power/raspberrypi-power.h>
++#include <soc/bcm2835/raspberrypi-firmware.h>
++
++/*
++ * Firmware indices for the old power domains interface. Only a few
++ * of them were actually implemented.
++ */
++#define RPI_OLD_POWER_DOMAIN_USB 3
++#define RPI_OLD_POWER_DOMAIN_V3D 10
++
++struct rpi_power_domain {
++ u32 domain;
++ bool enabled;
++ bool old_interface;
++ struct generic_pm_domain base;
++ struct rpi_firmware *fw;
++};
++
++struct rpi_power_domains {
++ bool has_new_interface;
++ struct genpd_onecell_data xlate;
++ struct rpi_firmware *fw;
++ struct rpi_power_domain domains[RPI_POWER_DOMAIN_COUNT];
++};
++
++/*
++ * Packet definition used by RPI_FIRMWARE_SET_POWER_STATE and
++ * RPI_FIRMWARE_SET_DOMAIN_STATE
++ */
++struct rpi_power_domain_packet {
++ u32 domain;
++ u32 on;
++} __packet;
++
++/*
++ * Asks the firmware to enable or disable power on a specific power
++ * domain.
++ */
++static int rpi_firmware_set_power(struct rpi_power_domain *rpi_domain, bool on)
++{
++ struct rpi_power_domain_packet packet;
++
++ packet.domain = rpi_domain->domain;
++ packet.on = on;
++ return rpi_firmware_property(rpi_domain->fw,
++ rpi_domain->old_interface ?
++ RPI_FIRMWARE_SET_POWER_STATE :
++ RPI_FIRMWARE_SET_DOMAIN_STATE,
++ &packet, sizeof(packet));
++}
++
++static int rpi_domain_off(struct generic_pm_domain *domain)
++{
++ struct rpi_power_domain *rpi_domain =
++ container_of(domain, struct rpi_power_domain, base);
++
++ return rpi_firmware_set_power(rpi_domain, false);
++}
++
++static int rpi_domain_on(struct generic_pm_domain *domain)
++{
++ struct rpi_power_domain *rpi_domain =
++ container_of(domain, struct rpi_power_domain, base);
++
++ return rpi_firmware_set_power(rpi_domain, true);
++}
++
++static void rpi_common_init_power_domain(struct rpi_power_domains *rpi_domains,
++ int xlate_index, const char *name)
++{
++ struct rpi_power_domain *dom = &rpi_domains->domains[xlate_index];
++
++ dom->fw = rpi_domains->fw;
++
++ dom->base.name = name;
++ dom->base.power_on = rpi_domain_on;
++ dom->base.power_off = rpi_domain_off;
++
++ /*
++ * Treat all power domains as off at boot.
++ *
++ * The firmware itself may be keeping some domains on, but
++ * from Linux's perspective all we control is the refcounts
++ * that we give to the firmware, and we can't ask the firmware
++ * to turn off something that we haven't ourselves turned on.
++ */
++ pm_genpd_init(&dom->base, NULL, true);
++
++ rpi_domains->xlate.domains[xlate_index] = &dom->base;
++}
++
++static void rpi_init_power_domain(struct rpi_power_domains *rpi_domains,
++ int xlate_index, const char *name)
++{
++ struct rpi_power_domain *dom = &rpi_domains->domains[xlate_index];
++
++ if (!rpi_domains->has_new_interface)
++ return;
++
++ /* The DT binding index is the firmware's domain index minus one. */
++ dom->domain = xlate_index + 1;
++
++ rpi_common_init_power_domain(rpi_domains, xlate_index, name);
++}
++
++static void rpi_init_old_power_domain(struct rpi_power_domains *rpi_domains,
++ int xlate_index, int domain,
++ const char *name)
++{
++ struct rpi_power_domain *dom = &rpi_domains->domains[xlate_index];
++
++ dom->old_interface = true;
++ dom->domain = domain;
++
++ rpi_common_init_power_domain(rpi_domains, xlate_index, name);
++}
++
++/*
++ * Detects whether the firmware supports the new power domains interface.
++ *
++ * The firmware doesn't actually return an error on an unknown tag,
++ * and just skips over it, so we do the detection by putting an
++ * unexpected value in the return field and checking if it was
++ * unchanged.
++ */
++static bool
++rpi_has_new_domain_support(struct rpi_power_domains *rpi_domains)
++{
++ struct rpi_power_domain_packet packet;
++ int ret;
++
++ packet.domain = RPI_POWER_DOMAIN_ARM;
++ packet.on = ~0;
++
++ ret = rpi_firmware_property(rpi_domains->fw,
++ RPI_FIRMWARE_GET_DOMAIN_STATE,
++ &packet, sizeof(packet));
++
++ return ret == 0 && packet.on != ~0;
++}
++
++static int rpi_power_probe(struct platform_device *pdev)
++{
++ struct device_node *fw_np;
++ struct device *dev = &pdev->dev;
++ struct rpi_power_domains *rpi_domains;
++
++ rpi_domains = devm_kzalloc(dev, sizeof(*rpi_domains), GFP_KERNEL);
++ if (!rpi_domains)
++ return -ENOMEM;
++
++ rpi_domains->xlate.domains =
++ devm_kzalloc(dev, sizeof(*rpi_domains->xlate.domains) *
++ RPI_POWER_DOMAIN_COUNT, GFP_KERNEL);
++ if (!rpi_domains->xlate.domains)
++ return -ENOMEM;
++
++ rpi_domains->xlate.num_domains = RPI_POWER_DOMAIN_COUNT;
++
++ fw_np = of_parse_phandle(pdev->dev.of_node, "firmware", 0);
++ if (!fw_np) {
++ dev_err(&pdev->dev, "no firmware node\n");
++ return -ENODEV;
++ }
++
++ rpi_domains->fw = rpi_firmware_get(fw_np);
++ of_node_put(fw_np);
++ if (!rpi_domains->fw)
++ return -EPROBE_DEFER;
++
++ rpi_domains->has_new_interface =
++ rpi_has_new_domain_support(rpi_domains);
++
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_I2C0, "I2C0");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_I2C1, "I2C1");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_I2C2, "I2C2");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_VIDEO_SCALER,
++ "VIDEO_SCALER");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_VPU1, "VPU1");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_HDMI, "HDMI");
++
++ /*
++ * Use the old firmware interface for USB power, so that we
++ * can turn it on even if the firmware hasn't been updated.
++ */
++ rpi_init_old_power_domain(rpi_domains, RPI_POWER_DOMAIN_USB,
++ RPI_OLD_POWER_DOMAIN_USB, "USB");
++
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_VEC, "VEC");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_JPEG, "JPEG");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_H264, "H264");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_V3D, "V3D");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_ISP, "ISP");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_UNICAM0, "UNICAM0");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_UNICAM1, "UNICAM1");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CCP2RX, "CCP2RX");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CSI2, "CSI2");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CPI, "CPI");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_DSI0, "DSI0");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_DSI1, "DSI1");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_TRANSPOSER,
++ "TRANSPOSER");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CCP2TX, "CCP2TX");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CDP, "CDP");
++ rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_ARM, "ARM");
++
++ of_genpd_add_provider_onecell(dev->of_node, &rpi_domains->xlate);
++
++ platform_set_drvdata(pdev, rpi_domains);
++
++ return 0;
++}
++
++static const struct of_device_id rpi_power_of_match[] = {
++ { .compatible = "raspberrypi,bcm2835-power", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rpi_power_of_match);
++
++static struct platform_driver rpi_power_driver = {
++ .driver = {
++ .name = "raspberrypi-power",
++ .of_match_table = rpi_power_of_match,
++ },
++ .probe = rpi_power_probe,
++};
++builtin_platform_driver(rpi_power_driver);
++
++MODULE_AUTHOR("Alexander Aring <aar@pengutronix.de>");
++MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
++MODULE_DESCRIPTION("Raspberry Pi power domain driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/include/dt-bindings/power/raspberrypi-power.h
+@@ -0,0 +1,41 @@
++/*
++ * Copyright © 2015 Broadcom
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
++#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
++
++/* These power domain indices are the firmware interface's indices
++ * minus one.
++ */
++#define RPI_POWER_DOMAIN_I2C0 0
++#define RPI_POWER_DOMAIN_I2C1 1
++#define RPI_POWER_DOMAIN_I2C2 2
++#define RPI_POWER_DOMAIN_VIDEO_SCALER 3
++#define RPI_POWER_DOMAIN_VPU1 4
++#define RPI_POWER_DOMAIN_HDMI 5
++#define RPI_POWER_DOMAIN_USB 6
++#define RPI_POWER_DOMAIN_VEC 7
++#define RPI_POWER_DOMAIN_JPEG 8
++#define RPI_POWER_DOMAIN_H264 9
++#define RPI_POWER_DOMAIN_V3D 10
++#define RPI_POWER_DOMAIN_ISP 11
++#define RPI_POWER_DOMAIN_UNICAM0 12
++#define RPI_POWER_DOMAIN_UNICAM1 13
++#define RPI_POWER_DOMAIN_CCP2RX 14
++#define RPI_POWER_DOMAIN_CSI2 15
++#define RPI_POWER_DOMAIN_CPI 16
++#define RPI_POWER_DOMAIN_DSI0 17
++#define RPI_POWER_DOMAIN_DSI1 18
++#define RPI_POWER_DOMAIN_TRANSPOSER 19
++#define RPI_POWER_DOMAIN_CCP2TX 20
++#define RPI_POWER_DOMAIN_CDP 21
++#define RPI_POWER_DOMAIN_ARM 22
++
++#define RPI_POWER_DOMAIN_COUNT 23
++
++#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */
--- /dev/null
+From ac82db5c0d1e26b32d285100e423a89b35e188da Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 31 Dec 2015 23:39:14 +0100
+Subject: [PATCH 270/304] ARM: bcm2835: clarify RASPBERRYPI_FIRMWARE dependency
+
+The firmware driver can be a loadable module, but the power domain
+can only be built-in, so we get a build error in an allmodconfig
+kernel:
+
+:(.text+0x17e59c): undefined reference to `rpi_firmware_property'
+:(.text+0x17e51c): undefined reference to `rpi_firmware_get'
+:(.text+0x17e244): undefined reference to `rpi_firmware_property'
+
+This changes the dependency to only allow the power domain code
+to be enabled when the firmware driver is built-in. Other users
+of the firmware driver may still be loadable modules and not
+everyone needs the power domains, so we don't change the firmware
+code.
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+(cherry picked from commit 22a5b1ddd83b991b96cb635898e011cce48bf6f8)
+---
+ drivers/soc/bcm/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/soc/bcm/Kconfig
++++ b/drivers/soc/bcm/Kconfig
+@@ -1,7 +1,7 @@
+ config RASPBERRYPI_POWER
+ bool "Raspberry Pi power domain driver"
+ depends on ARCH_BCM2835 || COMPILE_TEST
+- depends on RASPBERRYPI_FIRMWARE
++ depends on RASPBERRYPI_FIRMWARE=y
+ select PM_GENERIC_DOMAINS if PM
+ select PM_GENERIC_DOMAINS_OF if PM
+ help
--- /dev/null
+From 7d8d65cfc7508ec01431ead3e830d7d2f3886c05 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 19 Apr 2016 15:55:02 -0700
+Subject: [PATCH 271/304] ARM: bcm2708: Enable building power domain driver.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+---
+ drivers/soc/bcm/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/soc/bcm/Kconfig
++++ b/drivers/soc/bcm/Kconfig
+@@ -1,6 +1,6 @@
+ config RASPBERRYPI_POWER
+ bool "Raspberry Pi power domain driver"
+- depends on ARCH_BCM2835 || COMPILE_TEST
++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 || COMPILE_TEST
+ depends on RASPBERRYPI_FIRMWARE=y
+ select PM_GENERIC_DOMAINS if PM
+ select PM_GENERIC_DOMAINS_OF if PM
--- /dev/null
+From bf75d7a28fc441ac4be06169b3c4cba117e8fe65 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 19 Apr 2016 14:23:30 -0700
+Subject: [PATCH 272/304] bcm2708: Add RASPBERRYPI_POWER to the defconfigs.
+
+This will be used by the GPU driver for powering on HDMI at boot time
+and for 3D hang reset.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+---
+ arch/arm/configs/bcm2709_defconfig | 2 ++
+ arch/arm/configs/bcmrpi_defconfig | 2 ++
+ 2 files changed, 4 insertions(+)
+
+--- a/arch/arm/configs/bcm2709_defconfig
++++ b/arch/arm/configs/bcm2709_defconfig
+@@ -71,6 +71,7 @@ CONFIG_NEON=y
+ CONFIG_KERNEL_MODE_NEON=y
+ CONFIG_BINFMT_MISC=m
+ # CONFIG_SUSPEND is not set
++CONFIG_PM=y
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+ CONFIG_UNIX=y
+@@ -1116,6 +1117,7 @@ CONFIG_FB_TFT_FBTFT_DEVICE=m
+ CONFIG_MAILBOX=y
+ CONFIG_BCM2835_MBOX=y
+ # CONFIG_IOMMU_SUPPORT is not set
++CONFIG_RASPBERRYPI_POWER=y
+ CONFIG_EXTCON=m
+ CONFIG_EXTCON_ARIZONA=m
+ CONFIG_IIO=m
+--- a/arch/arm/configs/bcmrpi_defconfig
++++ b/arch/arm/configs/bcmrpi_defconfig
+@@ -64,6 +64,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+ CONFIG_VFP=y
+ CONFIG_BINFMT_MISC=m
+ # CONFIG_SUSPEND is not set
++CONFIG_PM=y
+ CONFIG_NET=y
+ CONFIG_PACKET=y
+ CONFIG_UNIX=y
+@@ -1123,6 +1124,7 @@ CONFIG_FB_TFT_FBTFT_DEVICE=m
+ CONFIG_MAILBOX=y
+ CONFIG_BCM2835_MBOX=y
+ # CONFIG_IOMMU_SUPPORT is not set
++CONFIG_RASPBERRYPI_POWER=y
+ CONFIG_EXTCON=m
+ CONFIG_EXTCON_ARIZONA=m
+ CONFIG_IIO=m
--- /dev/null
+From 2a94252c32f0235640f8f38b1222be411b8a43ae Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 19 Apr 2016 14:36:31 -0700
+Subject: [PATCH 273/304] bcm2708: Add the power domain driver to the device
+ tree.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+---
+ arch/arm/boot/dts/bcm2708_common.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm/boot/dts/bcm2708_common.dtsi
++++ b/arch/arm/boot/dts/bcm2708_common.dtsi
+@@ -285,6 +285,12 @@
+ mboxes = <&mailbox>;
+ };
+
++ power: power {
++ compatible = "raspberrypi,bcm2835-power";
++ firmware = <&firmware>;
++ #power-domain-cells = <1>;
++ };
++
+ leds: leds {
+ compatible = "gpio-leds";
+ };
--- /dev/null
+From c0415cdea10f5e9ab7f01e840500cb4aeb660ee5 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 19 Apr 2016 14:40:08 -0700
+Subject: [PATCH 274/304] bcm2708: Reference the HDMI power domain for the HDMI
+ driver.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+---
+ arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
++++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
+@@ -6,6 +6,7 @@
+ /plugin/;
+
+ #include "dt-bindings/clock/bcm2835.h"
++#include "dt-bindings/power/raspberrypi-power.h"
+ #include "dt-bindings/gpio/gpio.h"
+
+ / {
+@@ -72,6 +73,7 @@
+ clocks = <&cprman BCM2835_PLLH_PIX>,
+ <&cprman BCM2835_CLOCK_HSM>;
+ clock-names = "pixel", "hdmi";
++ power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+ };
+
+ v3d@7ec00000 {
--- /dev/null
+From 543efa41ce1be43b927ddbb6c999063f8f4f9caa Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Thu, 17 Dec 2015 15:36:28 +0300
+Subject: [PATCH 275/304] drm/vc4: copy_to_user() returns the number of bytes
+ remaining
+
+The copy_to/from_user() functions return the number of bytes remaining
+to be copied. We want to return error codes here.
+
+Also it's a bad idea to print an error message if a copy from user fails
+because users can use that to spam /var/log/messages which is annoying
+so I removed those.
+
+Fixes: 214613656b51 ('drm/vc4: Add an interface for capturing the GPU state after a hang.')
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 65c4777de54a39b2722a4b1ff3306d044014d511)
+---
+ drivers/gpu/drm/vc4/vc4_gem.c | 37 ++++++++++++++++++-------------------
+ 1 file changed, 18 insertions(+), 19 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_gem.c
++++ b/drivers/gpu/drm/vc4/vc4_gem.c
+@@ -85,7 +85,7 @@ vc4_get_hang_state_ioctl(struct drm_devi
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+ unsigned long irqflags;
+ u32 i;
+- int ret;
++ int ret = 0;
+
+ spin_lock_irqsave(&vc4->job_lock, irqflags);
+ kernel_state = vc4->hang_state;
+@@ -133,9 +133,11 @@ vc4_get_hang_state_ioctl(struct drm_devi
+ bo_state[i].size = vc4_bo->base.base.size;
+ }
+
+- ret = copy_to_user((void __user *)(uintptr_t)get_state->bo,
+- bo_state,
+- state->bo_count * sizeof(*bo_state));
++ if (copy_to_user((void __user *)(uintptr_t)get_state->bo,
++ bo_state,
++ state->bo_count * sizeof(*bo_state)))
++ ret = -EFAULT;
++
+ kfree(bo_state);
+
+ err_free:
+@@ -563,27 +565,24 @@ vc4_get_bcl(struct drm_device *dev, stru
+ exec->shader_state = temp + exec_size;
+ exec->shader_state_size = args->shader_rec_count;
+
+- ret = copy_from_user(bin,
+- (void __user *)(uintptr_t)args->bin_cl,
+- args->bin_cl_size);
+- if (ret) {
+- DRM_ERROR("Failed to copy in bin cl\n");
++ if (copy_from_user(bin,
++ (void __user *)(uintptr_t)args->bin_cl,
++ args->bin_cl_size)) {
++ ret = -EFAULT;
+ goto fail;
+ }
+
+- ret = copy_from_user(exec->shader_rec_u,
+- (void __user *)(uintptr_t)args->shader_rec,
+- args->shader_rec_size);
+- if (ret) {
+- DRM_ERROR("Failed to copy in shader recs\n");
++ if (copy_from_user(exec->shader_rec_u,
++ (void __user *)(uintptr_t)args->shader_rec,
++ args->shader_rec_size)) {
++ ret = -EFAULT;
+ goto fail;
+ }
+
+- ret = copy_from_user(exec->uniforms_u,
+- (void __user *)(uintptr_t)args->uniforms,
+- args->uniforms_size);
+- if (ret) {
+- DRM_ERROR("Failed to copy in uniforms cl\n");
++ if (copy_from_user(exec->uniforms_u,
++ (void __user *)(uintptr_t)args->uniforms,
++ args->uniforms_size)) {
++ ret = -EFAULT;
+ goto fail;
+ }
+
--- /dev/null
+From bedbbde45f7c1fce63e5f2c4e21bc9dd4e20f3c0 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Thu, 17 Dec 2015 15:39:08 +0300
+Subject: [PATCH 276/304] drm/vc4: allocate enough memory in
+ vc4_save_hang_state()
+
+"state" is smaller than "kernel_state" so we end up corrupting memory.
+
+Fixes: 214613656b51 ('drm/vc4: Add an interface for capturing the GPU state after a hang.')
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 7e5082fbc00cc157e57a70cdb6b9bbb21289afb1)
+---
+ drivers/gpu/drm/vc4/vc4_gem.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_gem.c
++++ b/drivers/gpu/drm/vc4/vc4_gem.c
+@@ -159,7 +159,7 @@ vc4_save_hang_state(struct drm_device *d
+ unsigned long irqflags;
+ unsigned int i, unref_list_count;
+
+- kernel_state = kcalloc(1, sizeof(*state), GFP_KERNEL);
++ kernel_state = kcalloc(1, sizeof(*kernel_state), GFP_KERNEL);
+ if (!kernel_state)
+ return;
+
--- /dev/null
+From a9d885719c6b17fe34cf4df2e7754aaeab352b4c Mon Sep 17 00:00:00 2001
+From: Dave Airlie <airlied@redhat.com>
+Date: Mon, 18 Jan 2016 09:10:42 +1000
+Subject: [PATCH 277/304] drm/vc4: fix warning in validate printf.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This just fixes a warning on 64-bit builds:
+
+ drivers/gpu/drm/vc4/vc4_validate.c: In function ‘validate_gl_shader_rec’:
+ drivers/gpu/drm/vc4/vc4_validate.c:864:12: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t {aka long unsigned int}’ [-Wformat=]
+
+Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+(cherry picked from commit c671e1e30259da587d7a0162895200601979ee65)
+---
+ drivers/gpu/drm/vc4/vc4_validate.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_validate.c
++++ b/drivers/gpu/drm/vc4/vc4_validate.c
+@@ -861,7 +861,7 @@ validate_gl_shader_rec(struct drm_device
+
+ if (vbo->base.size < offset ||
+ vbo->base.size - offset < attr_size) {
+- DRM_ERROR("BO offset overflow (%d + %d > %d)\n",
++ DRM_ERROR("BO offset overflow (%d + %d > %zu)\n",
+ offset, attr_size, vbo->base.size);
+ return -EINVAL;
+ }
--- /dev/null
+From 3049b5e72472a580753328c31e191fac5e3b151b Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 28 Dec 2015 14:14:09 -0800
+Subject: [PATCH 278/304] drm/vc4: Improve comments on vc4_plane_state members.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit f427fb16cf756548c39256b569cf083f39bcc4e9)
+---
+ drivers/gpu/drm/vc4/vc4_plane.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -26,16 +26,19 @@
+
+ struct vc4_plane_state {
+ struct drm_plane_state base;
++ /* System memory copy of the display list for this element, computed
++ * at atomic_check time.
++ */
+ u32 *dlist;
+- u32 dlist_size; /* Number of dwords in allocated for the display list */
++ u32 dlist_size; /* Number of dwords allocated for the display list */
+ u32 dlist_count; /* Number of used dwords in the display list. */
+
+ /* Offset in the dlist to pointer word 0. */
+ u32 pw0_offset;
+
+ /* Offset where the plane's dlist was last stored in the
+- hardware at vc4_crtc_atomic_flush() time.
+- */
++ * hardware at vc4_crtc_atomic_flush() time.
++ */
+ u32 *hw_dlist;
+ };
+
--- /dev/null
+From 3bf29123a33a5f8c786e35e12310d82b61c68237 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 28 Dec 2015 14:14:57 -0800
+Subject: [PATCH 279/304] drm/vc4: Add missing __iomem annotation to hw_dlist.
+
+This is the pointer to the HVS device's memory where we stored the
+contents of *dlist.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 17eac75111ebda33e13d8d8d98aaedfc1a9c2abf)
+---
+ drivers/gpu/drm/vc4/vc4_plane.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -39,7 +39,7 @@ struct vc4_plane_state {
+ /* Offset where the plane's dlist was last stored in the
+ * hardware at vc4_crtc_atomic_flush() time.
+ */
+- u32 *hw_dlist;
++ u32 __iomem *hw_dlist;
+ };
+
+ static inline struct vc4_plane_state *
--- /dev/null
+From 85b7377efcfbf19aa6b0602ba3aa501ce7e7c9bd Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 28 Dec 2015 14:34:44 -0800
+Subject: [PATCH 280/304] drm/vc4: Move the plane clipping/scaling setup to a
+ separate function.
+
+As we add actual scaling, this is going to get way more complicated.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 5c6799942003df91801b1d2277bba34d71f99603)
+---
+ drivers/gpu/drm/vc4/vc4_plane.c | 78 +++++++++++++++++++++++++++--------------
+ 1 file changed, 52 insertions(+), 26 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -40,6 +40,14 @@ struct vc4_plane_state {
+ * hardware at vc4_crtc_atomic_flush() time.
+ */
+ u32 __iomem *hw_dlist;
++
++ /* Clipped coordinates of the plane on the display. */
++ int crtc_x, crtc_y, crtc_w, crtc_h;
++
++ /* Offset to start scanning out from the start of the plane's
++ * BO.
++ */
++ u32 offset;
+ };
+
+ static inline struct vc4_plane_state *
+@@ -167,22 +175,17 @@ static void vc4_dlist_write(struct vc4_p
+ vc4_state->dlist[vc4_state->dlist_count++] = val;
+ }
+
+-/* Writes out a full display list for an active plane to the plane's
+- * private dlist state.
+- */
+-static int vc4_plane_mode_set(struct drm_plane *plane,
+- struct drm_plane_state *state)
++static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
+ {
+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+ struct drm_framebuffer *fb = state->fb;
+- struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
+- u32 ctl0_offset = vc4_state->dlist_count;
+- const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);
+- uint32_t offset = fb->offsets[0];
+- int crtc_x = state->crtc_x;
+- int crtc_y = state->crtc_y;
+- int crtc_w = state->crtc_w;
+- int crtc_h = state->crtc_h;
++
++ vc4_state->offset = fb->offsets[0];
++
++ vc4_state->crtc_x = state->crtc_x;
++ vc4_state->crtc_y = state->crtc_y;
++ vc4_state->crtc_w = state->crtc_w;
++ vc4_state->crtc_h = state->crtc_h;
+
+ if (state->crtc_w << 16 != state->src_w ||
+ state->crtc_h << 16 != state->src_h) {
+@@ -194,18 +197,41 @@ static int vc4_plane_mode_set(struct drm
+ return -EINVAL;
+ }
+
+- if (crtc_x < 0) {
+- offset += drm_format_plane_cpp(fb->pixel_format, 0) * -crtc_x;
+- crtc_w += crtc_x;
+- crtc_x = 0;
++ if (vc4_state->crtc_x < 0) {
++ vc4_state->offset += (drm_format_plane_cpp(fb->pixel_format,
++ 0) *
++ -vc4_state->crtc_x);
++ vc4_state->crtc_w += vc4_state->crtc_x;
++ vc4_state->crtc_x = 0;
+ }
+
+- if (crtc_y < 0) {
+- offset += fb->pitches[0] * -crtc_y;
+- crtc_h += crtc_y;
+- crtc_y = 0;
++ if (vc4_state->crtc_y < 0) {
++ vc4_state->offset += fb->pitches[0] * -vc4_state->crtc_y;
++ vc4_state->crtc_h += vc4_state->crtc_y;
++ vc4_state->crtc_y = 0;
+ }
+
++ return 0;
++}
++
++
++/* Writes out a full display list for an active plane to the plane's
++ * private dlist state.
++ */
++static int vc4_plane_mode_set(struct drm_plane *plane,
++ struct drm_plane_state *state)
++{
++ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
++ struct drm_framebuffer *fb = state->fb;
++ struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
++ u32 ctl0_offset = vc4_state->dlist_count;
++ const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);
++ int ret;
++
++ ret = vc4_plane_setup_clipping_and_scaling(state);
++ if (ret)
++ return ret;
++
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+@@ -215,8 +241,8 @@ static int vc4_plane_mode_set(struct drm
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(0xff, SCALER_POS0_FIXED_ALPHA) |
+- VC4_SET_FIELD(crtc_x, SCALER_POS0_START_X) |
+- VC4_SET_FIELD(crtc_y, SCALER_POS0_START_Y));
++ VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
++ VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
+
+ /* Position Word 1: Scaled Image Dimensions.
+ * Skipped due to SCALER_CTL0_UNITY scaling.
+@@ -228,8 +254,8 @@ static int vc4_plane_mode_set(struct drm
+ SCALER_POS2_ALPHA_MODE_PIPELINE :
+ SCALER_POS2_ALPHA_MODE_FIXED,
+ SCALER_POS2_ALPHA_MODE) |
+- VC4_SET_FIELD(crtc_w, SCALER_POS2_WIDTH) |
+- VC4_SET_FIELD(crtc_h, SCALER_POS2_HEIGHT));
++ VC4_SET_FIELD(vc4_state->crtc_w, SCALER_POS2_WIDTH) |
++ VC4_SET_FIELD(vc4_state->crtc_h, SCALER_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+@@ -237,7 +263,7 @@ static int vc4_plane_mode_set(struct drm
+ vc4_state->pw0_offset = vc4_state->dlist_count;
+
+ /* Pointer Word 0: RGB / Y Pointer */
+- vc4_dlist_write(vc4_state, bo->paddr + offset);
++ vc4_dlist_write(vc4_state, bo->paddr + vc4_state->offset);
+
+ /* Pointer Context Word 0: Written by the HVS */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
--- /dev/null
+From a53e75a061bbfb0bb24128a2a9c9961ec20e22ec Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Wed, 30 Dec 2015 11:50:22 -0800
+Subject: [PATCH 281/304] drm/vc4: Add a proper short-circut path for legacy
+ cursor updates.
+
+Previously, on every modeset we would allocate new display list
+memory, recompute changed planes, write all of them to the new memory,
+and pointed scanout at the new list (which will latch approximately at
+the next line of scanout). We let
+drm_atomic_helper_wait_for_vblanks() decide whether we needed to wait
+for a vblank after a modeset before cleaning up the old state and
+letting the next modeset proceed, and on legacy cursor updates we
+wouldn't wait. If you moved the cursor fast enough, we could
+potentially wrap around the display list memory area and overwrite the
+existing display list while it was still being scanned out, resulting
+in the HVS scanning out garbage or just halting.
+
+Instead of making cursor updates wait for scanout to move to the new
+display list area (which introduces significant cursor lag in X), we
+just rewrite our current display list.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 6674a904d68041d982ffb284d2827410765a097a)
+---
+ drivers/gpu/drm/vc4/vc4_kms.c | 9 ++++
+ drivers/gpu/drm/vc4/vc4_plane.c | 94 ++++++++++++++++++++++++++++++++++++++---
+ 2 files changed, 96 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_kms.c
++++ b/drivers/gpu/drm/vc4/vc4_kms.c
+@@ -49,6 +49,15 @@ vc4_atomic_complete_commit(struct vc4_co
+
+ drm_atomic_helper_commit_modeset_enables(dev, state);
+
++ /* Make sure that drm_atomic_helper_wait_for_vblanks()
++ * actually waits for vblank. If we're doing a full atomic
++ * modeset (as opposed to a vc4_update_plane() short circuit),
++ * then we need to wait for scanout to be done with our
++ * display lists before we free it and potentially reallocate
++ * and overwrite the dlist memory with a new modeset.
++ */
++ state->legacy_cursor_update = false;
++
+ drm_atomic_helper_wait_for_vblanks(dev, state);
+
+ drm_atomic_helper_cleanup_planes(dev, state);
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -33,8 +33,12 @@ struct vc4_plane_state {
+ u32 dlist_size; /* Number of dwords allocated for the display list */
+ u32 dlist_count; /* Number of used dwords in the display list. */
+
+- /* Offset in the dlist to pointer word 0. */
+- u32 pw0_offset;
++ /* Offset in the dlist to various words, for pageflip or
++ * cursor updates.
++ */
++ u32 pos0_offset;
++ u32 pos2_offset;
++ u32 ptr0_offset;
+
+ /* Offset where the plane's dlist was last stored in the
+ * hardware at vc4_crtc_atomic_flush() time.
+@@ -239,6 +243,7 @@ static int vc4_plane_mode_set(struct drm
+ SCALER_CTL0_UNITY);
+
+ /* Position Word 0: Image Positions and Alpha Value */
++ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(0xff, SCALER_POS0_FIXED_ALPHA) |
+ VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
+@@ -249,6 +254,7 @@ static int vc4_plane_mode_set(struct drm
+ */
+
+ /* Position Word 2: Source Image Size, Alpha Mode */
++ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(format->has_alpha ?
+ SCALER_POS2_ALPHA_MODE_PIPELINE :
+@@ -260,9 +266,8 @@ static int vc4_plane_mode_set(struct drm
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+
+- vc4_state->pw0_offset = vc4_state->dlist_count;
+-
+ /* Pointer Word 0: RGB / Y Pointer */
++ vc4_state->ptr0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state, bo->paddr + vc4_state->offset);
+
+ /* Pointer Context Word 0: Written by the HVS */
+@@ -348,13 +353,13 @@ void vc4_plane_async_set_fb(struct drm_p
+ * scanout will start from this address as soon as the FIFO
+ * needs to refill with pixels.
+ */
+- writel(addr, &vc4_state->hw_dlist[vc4_state->pw0_offset]);
++ writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
+
+ /* Also update the CPU-side dlist copy, so that any later
+ * atomic updates that don't do a new modeset on our plane
+ * also use our updated address.
+ */
+- vc4_state->dlist[vc4_state->pw0_offset] = addr;
++ vc4_state->dlist[vc4_state->ptr0_offset] = addr;
+ }
+
+ static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
+@@ -370,8 +375,83 @@ static void vc4_plane_destroy(struct drm
+ drm_plane_cleanup(plane);
+ }
+
++/* Implements immediate (non-vblank-synced) updates of the cursor
++ * position, or falls back to the atomic helper otherwise.
++ */
++static int
++vc4_update_plane(struct drm_plane *plane,
++ struct drm_crtc *crtc,
++ struct drm_framebuffer *fb,
++ int crtc_x, int crtc_y,
++ unsigned int crtc_w, unsigned int crtc_h,
++ uint32_t src_x, uint32_t src_y,
++ uint32_t src_w, uint32_t src_h)
++{
++ struct drm_plane_state *plane_state;
++ struct vc4_plane_state *vc4_state;
++
++ if (plane != crtc->cursor)
++ goto out;
++
++ plane_state = plane->state;
++ vc4_state = to_vc4_plane_state(plane_state);
++
++ if (!plane_state)
++ goto out;
++
++ /* If we're changing the cursor contents, do that in the
++ * normal vblank-synced atomic path.
++ */
++ if (fb != plane_state->fb)
++ goto out;
++
++ /* No configuring new scaling in the fast path. */
++ if (crtc_w != plane_state->crtc_w ||
++ crtc_h != plane_state->crtc_h ||
++ src_w != plane_state->src_w ||
++ src_h != plane_state->src_h) {
++ goto out;
++ }
++
++ /* Set the cursor's position on the screen. This is the
++ * expected change from the drm_mode_cursor_universal()
++ * helper.
++ */
++ plane_state->crtc_x = crtc_x;
++ plane_state->crtc_y = crtc_y;
++
++ /* Allow changing the start position within the cursor BO, if
++ * that matters.
++ */
++ plane_state->src_x = src_x;
++ plane_state->src_y = src_y;
++
++ /* Update the display list based on the new crtc_x/y. */
++ vc4_plane_atomic_check(plane, plane_state);
++
++ /* Note that we can't just call vc4_plane_write_dlist()
++ * because that would smash the context data that the HVS is
++ * currently using.
++ */
++ writel(vc4_state->dlist[vc4_state->pos0_offset],
++ &vc4_state->hw_dlist[vc4_state->pos0_offset]);
++ writel(vc4_state->dlist[vc4_state->pos2_offset],
++ &vc4_state->hw_dlist[vc4_state->pos2_offset]);
++ writel(vc4_state->dlist[vc4_state->ptr0_offset],
++ &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
++
++ return 0;
++
++out:
++ return drm_atomic_helper_update_plane(plane, crtc, fb,
++ crtc_x, crtc_y,
++ crtc_w, crtc_h,
++ src_x, src_y,
++ src_w, src_h);
++}
++
+ static const struct drm_plane_funcs vc4_plane_funcs = {
+- .update_plane = drm_atomic_helper_update_plane,
++ .update_plane = vc4_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = vc4_plane_destroy,
+ .set_property = NULL,
--- /dev/null
+From 85d92a47f1a200de3ea7cd0a3d790b2a286ade40 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 28 Dec 2015 13:25:41 -0800
+Subject: [PATCH 282/304] drm/vc4: Make the CRTCs cooperate on allocating
+ display lists.
+
+So far, we've only ever lit up one CRTC, so this has been fine. To
+extend to more displays or more planes, we need to make sure we don't
+run our display lists into each other.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit d8dbf44f13b91185c618219d912b246817a8d132)
+---
+ drivers/gpu/drm/vc4/vc4_crtc.c | 115 +++++++++++++++++++++++------------------
+ drivers/gpu/drm/vc4/vc4_drv.h | 8 ++-
+ drivers/gpu/drm/vc4/vc4_hvs.c | 13 +++++
+ 3 files changed, 84 insertions(+), 52 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_crtc.c
++++ b/drivers/gpu/drm/vc4/vc4_crtc.c
+@@ -49,22 +49,27 @@ struct vc4_crtc {
+ /* Which HVS channel we're using for our CRTC. */
+ int channel;
+
+- /* Pointer to the actual hardware display list memory for the
+- * crtc.
+- */
+- u32 __iomem *dlist;
+-
+- u32 dlist_size; /* in dwords */
+-
+ struct drm_pending_vblank_event *event;
+ };
+
++struct vc4_crtc_state {
++ struct drm_crtc_state base;
++ /* Dlist area for this CRTC configuration. */
++ struct drm_mm_node mm;
++};
++
+ static inline struct vc4_crtc *
+ to_vc4_crtc(struct drm_crtc *crtc)
+ {
+ return (struct vc4_crtc *)crtc;
+ }
+
++static inline struct vc4_crtc_state *
++to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
++{
++ return (struct vc4_crtc_state *)crtc_state;
++}
++
+ struct vc4_crtc_data {
+ /* Which channel of the HVS this pixelvalve sources from. */
+ int hvs_channel;
+@@ -319,11 +324,13 @@ static void vc4_crtc_enable(struct drm_c
+ static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
+ struct drm_crtc_state *state)
+ {
++ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
+ struct drm_device *dev = crtc->dev;
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct drm_plane *plane;
+- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
++ unsigned long flags;
+ u32 dlist_count = 0;
++ int ret;
+
+ /* The pixelvalve can only feed one encoder (and encoders are
+ * 1:1 with connectors.)
+@@ -346,18 +353,12 @@ static int vc4_crtc_atomic_check(struct
+
+ dlist_count++; /* Account for SCALER_CTL0_END. */
+
+- if (!vc4_crtc->dlist || dlist_count > vc4_crtc->dlist_size) {
+- vc4_crtc->dlist = ((u32 __iomem *)vc4->hvs->dlist +
+- HVS_BOOTLOADER_DLIST_END);
+- vc4_crtc->dlist_size = ((SCALER_DLIST_SIZE >> 2) -
+- HVS_BOOTLOADER_DLIST_END);
+-
+- if (dlist_count > vc4_crtc->dlist_size) {
+- DRM_DEBUG_KMS("dlist too large for CRTC (%d > %d).\n",
+- dlist_count, vc4_crtc->dlist_size);
+- return -EINVAL;
+- }
+- }
++ spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
++ ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
++ dlist_count, 1, 0);
++ spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
++ if (ret)
++ return ret;
+
+ return 0;
+ }
+@@ -368,47 +369,29 @@ static void vc4_crtc_atomic_flush(struct
+ struct drm_device *dev = crtc->dev;
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
++ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
+ struct drm_plane *plane;
+ bool debug_dump_regs = false;
+- u32 __iomem *dlist_next = vc4_crtc->dlist;
++ u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
++ u32 __iomem *dlist_next = dlist_start;
+
+ if (debug_dump_regs) {
+ DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
+ vc4_hvs_dump_state(dev);
+ }
+
+- /* Copy all the active planes' dlist contents to the hardware dlist.
+- *
+- * XXX: If the new display list was large enough that it
+- * overlapped a currently-read display list, we need to do
+- * something like disable scanout before putting in the new
+- * list. For now, we're safe because we only have the two
+- * planes.
+- */
++ /* Copy all the active planes' dlist contents to the hardware dlist. */
+ drm_atomic_crtc_for_each_plane(plane, crtc) {
+ dlist_next += vc4_plane_write_dlist(plane, dlist_next);
+ }
+
+- if (dlist_next == vc4_crtc->dlist) {
+- /* If no planes were enabled, use the SCALER_CTL0_END
+- * at the start of the display list memory (in the
+- * bootloader section). We'll rewrite that
+- * SCALER_CTL0_END, just in case, though.
+- */
+- writel(SCALER_CTL0_END, vc4->hvs->dlist);
+- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 0);
+- } else {
+- writel(SCALER_CTL0_END, dlist_next);
+- dlist_next++;
+-
+- HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
+- (u32 __iomem *)vc4_crtc->dlist -
+- (u32 __iomem *)vc4->hvs->dlist);
+-
+- /* Make the next display list start after ours. */
+- vc4_crtc->dlist_size -= (dlist_next - vc4_crtc->dlist);
+- vc4_crtc->dlist = dlist_next;
+- }
++ writel(SCALER_CTL0_END, dlist_next);
++ dlist_next++;
++
++ WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
++
++ HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
++ vc4_state->mm.start);
+
+ if (debug_dump_regs) {
+ DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
+@@ -573,6 +556,36 @@ static int vc4_page_flip(struct drm_crtc
+ return drm_atomic_helper_page_flip(crtc, fb, event, flags);
+ }
+
++static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
++{
++ struct vc4_crtc_state *vc4_state;
++
++ vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
++ if (!vc4_state)
++ return NULL;
++
++ __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
++ return &vc4_state->base;
++}
++
++static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
++ struct drm_crtc_state *state)
++{
++ struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
++ struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
++
++ if (vc4_state->mm.allocated) {
++ unsigned long flags;
++
++ spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
++ drm_mm_remove_node(&vc4_state->mm);
++ spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
++
++ }
++
++ __drm_atomic_helper_crtc_destroy_state(crtc, state);
++}
++
+ static const struct drm_crtc_funcs vc4_crtc_funcs = {
+ .set_config = drm_atomic_helper_set_config,
+ .destroy = vc4_crtc_destroy,
+@@ -581,8 +594,8 @@ static const struct drm_crtc_funcs vc4_c
+ .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
+ .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
+ .reset = drm_atomic_helper_crtc_reset,
+- .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+- .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
++ .atomic_duplicate_state = vc4_crtc_duplicate_state,
++ .atomic_destroy_state = vc4_crtc_destroy_state,
+ };
+
+ static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
+--- a/drivers/gpu/drm/vc4/vc4_drv.h
++++ b/drivers/gpu/drm/vc4/vc4_drv.h
+@@ -150,7 +150,13 @@ struct vc4_v3d {
+ struct vc4_hvs {
+ struct platform_device *pdev;
+ void __iomem *regs;
+- void __iomem *dlist;
++ u32 __iomem *dlist;
++
++ /* Memory manager for CRTCs to allocate space in the display
++ * list. Units are dwords.
++ */
++ struct drm_mm dlist_mm;
++ spinlock_t mm_lock;
+ };
+
+ struct vc4_plane {
+--- a/drivers/gpu/drm/vc4/vc4_hvs.c
++++ b/drivers/gpu/drm/vc4/vc4_hvs.c
+@@ -119,6 +119,17 @@ static int vc4_hvs_bind(struct device *d
+
+ hvs->dlist = hvs->regs + SCALER_DLIST_START;
+
++ spin_lock_init(&hvs->mm_lock);
++
++ /* Set up the HVS display list memory manager. We never
++ * overwrite the setup from the bootloader (just 128b out of
++ * our 16K), since we don't want to scramble the screen when
++ * transitioning from the firmware's boot setup to runtime.
++ */
++ drm_mm_init(&hvs->dlist_mm,
++ HVS_BOOTLOADER_DLIST_END,
++ (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
++
+ vc4->hvs = hvs;
+ return 0;
+ }
+@@ -129,6 +140,8 @@ static void vc4_hvs_unbind(struct device
+ struct drm_device *drm = dev_get_drvdata(master);
+ struct vc4_dev *vc4 = drm->dev_private;
+
++ drm_mm_takedown(&vc4->hvs->dlist_mm);
++
+ vc4->hvs = NULL;
+ }
+
--- /dev/null
+From 340763d1863fe246b44405edeba01889c81e5cb7 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 20 Oct 2015 14:18:56 +0100
+Subject: [PATCH 283/304] drm/vc4: Add more display planes to each CRTC.
+
+Previously we only did the primary and cursor plane, but overlay
+planes are useful and just require this setup to add, since all planes
+go into the HVS display list in the same way.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit fc2d6f1eabee9d971453da2a27a72471c2a347dd)
+---
+ drivers/gpu/drm/vc4/vc4_crtc.c | 56 ++++++++++++++++++++++++++++++------------
+ 1 file changed, 40 insertions(+), 16 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_crtc.c
++++ b/drivers/gpu/drm/vc4/vc4_crtc.c
+@@ -677,9 +677,9 @@ static int vc4_crtc_bind(struct device *
+ struct vc4_dev *vc4 = to_vc4_dev(drm);
+ struct vc4_crtc *vc4_crtc;
+ struct drm_crtc *crtc;
+- struct drm_plane *primary_plane, *cursor_plane;
++ struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
+ const struct of_device_id *match;
+- int ret;
++ int ret, i;
+
+ vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
+ if (!vc4_crtc)
+@@ -708,27 +708,49 @@ static int vc4_crtc_bind(struct device *
+ goto err;
+ }
+
+- cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
+- if (IS_ERR(cursor_plane)) {
+- dev_err(dev, "failed to construct cursor plane\n");
+- ret = PTR_ERR(cursor_plane);
+- goto err_primary;
+- }
+-
+- drm_crtc_init_with_planes(drm, crtc, primary_plane, cursor_plane,
++ drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
+ &vc4_crtc_funcs);
+ drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
+ primary_plane->crtc = crtc;
+- cursor_plane->crtc = crtc;
+ vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
+ vc4_crtc->channel = vc4_crtc->data->hvs_channel;
+
++ /* Set up some arbitrary number of planes. We're not limited
++ * by a set number of physical registers, just the space in
++ * the HVS (16k) and how small an plane can be (28 bytes).
++ * However, each plane we set up takes up some memory, and
++ * increases the cost of looping over planes, which atomic
++ * modesetting does quite a bit. As a result, we pick a
++ * modest number of planes to expose, that should hopefully
++ * still cover any sane usecase.
++ */
++ for (i = 0; i < 8; i++) {
++ struct drm_plane *plane =
++ vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
++
++ if (IS_ERR(plane))
++ continue;
++
++ plane->possible_crtcs = 1 << drm_crtc_index(crtc);
++ }
++
++ /* Set up the legacy cursor after overlay initialization,
++ * since we overlay planes on the CRTC in the order they were
++ * initialized.
++ */
++ cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
++ if (!IS_ERR(cursor_plane)) {
++ cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
++ cursor_plane->crtc = crtc;
++ crtc->cursor = cursor_plane;
++ }
++
+ CRTC_WRITE(PV_INTEN, 0);
+ CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
+ ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
+ vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
+ if (ret)
+- goto err_cursor;
++ goto err_destroy_planes;
+
+ vc4_set_crtc_possible_masks(drm, crtc);
+
+@@ -736,10 +758,12 @@ static int vc4_crtc_bind(struct device *
+
+ return 0;
+
+-err_cursor:
+- cursor_plane->funcs->destroy(cursor_plane);
+-err_primary:
+- primary_plane->funcs->destroy(primary_plane);
++err_destroy_planes:
++ list_for_each_entry_safe(destroy_plane, temp,
++ &drm->mode_config.plane_list, head) {
++ if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
++ destroy_plane->funcs->destroy(destroy_plane);
++ }
+ err:
+ return ret;
+ }
--- /dev/null
+From 309b7268e9cc7baa21d195cc98387cb984720185 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 28 Dec 2015 14:45:25 -0800
+Subject: [PATCH 284/304] drm/vc4: Fix which value is being used for source
+ image size.
+
+This doesn't matter yet since we only allow 1:1 scaling, but the
+comment clearly says we should be using the source size.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit f863e356013d628fa65b1cd89aa298eed26fc936)
+---
+ drivers/gpu/drm/vc4/vc4_plane.c | 23 ++++++++++++++---------
+ 1 file changed, 14 insertions(+), 9 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -47,6 +47,8 @@ struct vc4_plane_state {
+
+ /* Clipped coordinates of the plane on the display. */
+ int crtc_x, crtc_y, crtc_w, crtc_h;
++ /* Clipped size of the area scanned from in the FB. */
++ u32 src_w, src_h;
+
+ /* Offset to start scanning out from the start of the plane's
+ * BO.
+@@ -186,11 +188,6 @@ static int vc4_plane_setup_clipping_and_
+
+ vc4_state->offset = fb->offsets[0];
+
+- vc4_state->crtc_x = state->crtc_x;
+- vc4_state->crtc_y = state->crtc_y;
+- vc4_state->crtc_w = state->crtc_w;
+- vc4_state->crtc_h = state->crtc_h;
+-
+ if (state->crtc_w << 16 != state->src_w ||
+ state->crtc_h << 16 != state->src_h) {
+ /* We don't support scaling yet, which involves
+@@ -201,17 +198,25 @@ static int vc4_plane_setup_clipping_and_
+ return -EINVAL;
+ }
+
++ vc4_state->src_w = state->src_w >> 16;
++ vc4_state->src_h = state->src_h >> 16;
++
++ vc4_state->crtc_x = state->crtc_x;
++ vc4_state->crtc_y = state->crtc_y;
++ vc4_state->crtc_w = state->crtc_w;
++ vc4_state->crtc_h = state->crtc_h;
++
+ if (vc4_state->crtc_x < 0) {
+ vc4_state->offset += (drm_format_plane_cpp(fb->pixel_format,
+ 0) *
+ -vc4_state->crtc_x);
+- vc4_state->crtc_w += vc4_state->crtc_x;
++ vc4_state->src_w += vc4_state->crtc_x;
+ vc4_state->crtc_x = 0;
+ }
+
+ if (vc4_state->crtc_y < 0) {
+ vc4_state->offset += fb->pitches[0] * -vc4_state->crtc_y;
+- vc4_state->crtc_h += vc4_state->crtc_y;
++ vc4_state->src_h += vc4_state->crtc_y;
+ vc4_state->crtc_y = 0;
+ }
+
+@@ -260,8 +265,8 @@ static int vc4_plane_mode_set(struct drm
+ SCALER_POS2_ALPHA_MODE_PIPELINE :
+ SCALER_POS2_ALPHA_MODE_FIXED,
+ SCALER_POS2_ALPHA_MODE) |
+- VC4_SET_FIELD(vc4_state->crtc_w, SCALER_POS2_WIDTH) |
+- VC4_SET_FIELD(vc4_state->crtc_h, SCALER_POS2_HEIGHT));
++ VC4_SET_FIELD(vc4_state->src_w, SCALER_POS2_WIDTH) |
++ VC4_SET_FIELD(vc4_state->src_h, SCALER_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
--- /dev/null
+From 82360945a8104336f585180cd8d9c5fe4099d94b Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 20 Oct 2015 16:06:57 +0100
+Subject: [PATCH 285/304] drm/vc4: Add support for scaling of display planes.
+
+This implements a simple policy for choosing scaling modes
+(trapezoidal for decimation, PPF for magnification), and a single PPF
+filter (Mitchell/Netravali's recommendation).
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 21af94cf1a4c2d3450ab7fead58e6e2291ab92a9)
+---
+ drivers/gpu/drm/vc4/vc4_drv.h | 4 +
+ drivers/gpu/drm/vc4/vc4_hvs.c | 84 +++++++++++++
+ drivers/gpu/drm/vc4/vc4_plane.c | 253 +++++++++++++++++++++++++++++++++++++---
+ drivers/gpu/drm/vc4/vc4_regs.h | 46 ++++++++
+ 4 files changed, 374 insertions(+), 13 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_drv.h
++++ b/drivers/gpu/drm/vc4/vc4_drv.h
+@@ -156,7 +156,11 @@ struct vc4_hvs {
+ * list. Units are dwords.
+ */
+ struct drm_mm dlist_mm;
++ /* Memory manager for the LBM memory used by HVS scaling. */
++ struct drm_mm lbm_mm;
+ spinlock_t mm_lock;
++
++ struct drm_mm_node mitchell_netravali_filter;
+ };
+
+ struct vc4_plane {
+--- a/drivers/gpu/drm/vc4/vc4_hvs.c
++++ b/drivers/gpu/drm/vc4/vc4_hvs.c
+@@ -100,12 +100,76 @@ int vc4_hvs_debugfs_regs(struct seq_file
+ }
+ #endif
+
++/* The filter kernel is composed of dwords each containing 3 9-bit
++ * signed integers packed next to each other.
++ */
++#define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
++#define VC4_PPF_FILTER_WORD(c0, c1, c2) \
++ ((((c0) & 0x1ff) << 0) | \
++ (((c1) & 0x1ff) << 9) | \
++ (((c2) & 0x1ff) << 18))
++
++/* The whole filter kernel is arranged as the coefficients 0-16 going
++ * up, then a pad, then 17-31 going down and reversed within the
++ * dwords. This means that a linear phase kernel (where it's
++ * symmetrical at the boundary between 15 and 16) has the last 5
++ * dwords matching the first 5, but reversed.
++ */
++#define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \
++ c9, c10, c11, c12, c13, c14, c15) \
++ {VC4_PPF_FILTER_WORD(c0, c1, c2), \
++ VC4_PPF_FILTER_WORD(c3, c4, c5), \
++ VC4_PPF_FILTER_WORD(c6, c7, c8), \
++ VC4_PPF_FILTER_WORD(c9, c10, c11), \
++ VC4_PPF_FILTER_WORD(c12, c13, c14), \
++ VC4_PPF_FILTER_WORD(c15, c15, 0)}
++
++#define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
++#define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
++
++/* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
++ * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
++ */
++static const u32 mitchell_netravali_1_3_1_3_kernel[] =
++ VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
++ 50, 82, 119, 155, 187, 213, 227);
++
++static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
++ struct drm_mm_node *space,
++ const u32 *kernel)
++{
++ int ret, i;
++ u32 __iomem *dst_kernel;
++
++ ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS, 1,
++ 0);
++ if (ret) {
++ DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
++ ret);
++ return ret;
++ }
++
++ dst_kernel = hvs->dlist + space->start;
++
++ for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
++ if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
++ writel(kernel[i], &dst_kernel[i]);
++ else {
++ writel(kernel[VC4_KERNEL_DWORDS - i - 1],
++ &dst_kernel[i]);
++ }
++ }
++
++ return 0;
++}
++
+ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
+ {
+ struct platform_device *pdev = to_platform_device(dev);
+ struct drm_device *drm = dev_get_drvdata(master);
+ struct vc4_dev *vc4 = drm->dev_private;
+ struct vc4_hvs *hvs = NULL;
++ int ret;
+
+ hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
+ if (!hvs)
+@@ -130,6 +194,22 @@ static int vc4_hvs_bind(struct device *d
+ HVS_BOOTLOADER_DLIST_END,
+ (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
+
++ /* Set up the HVS LBM memory manager. We could have some more
++ * complicated data structure that allowed reuse of LBM areas
++ * between planes when they don't overlap on the screen, but
++ * for now we just allocate globally.
++ */
++ drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
++
++ /* Upload filter kernels. We only have the one for now, so we
++ * keep it around for the lifetime of the driver.
++ */
++ ret = vc4_hvs_upload_linear_kernel(hvs,
++ &hvs->mitchell_netravali_filter,
++ mitchell_netravali_1_3_1_3_kernel);
++ if (ret)
++ return ret;
++
+ vc4->hvs = hvs;
+ return 0;
+ }
+@@ -140,7 +220,11 @@ static void vc4_hvs_unbind(struct device
+ struct drm_device *drm = dev_get_drvdata(master);
+ struct vc4_dev *vc4 = drm->dev_private;
+
++ if (vc4->hvs->mitchell_netravali_filter.allocated)
++ drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
++
+ drm_mm_takedown(&vc4->hvs->dlist_mm);
++ drm_mm_takedown(&vc4->hvs->lbm_mm);
+
+ vc4->hvs = NULL;
+ }
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -24,6 +24,12 @@
+ #include "drm_fb_cma_helper.h"
+ #include "drm_plane_helper.h"
+
++enum vc4_scaling_mode {
++ VC4_SCALING_NONE,
++ VC4_SCALING_TPZ,
++ VC4_SCALING_PPF,
++};
++
+ struct vc4_plane_state {
+ struct drm_plane_state base;
+ /* System memory copy of the display list for this element, computed
+@@ -47,13 +53,19 @@ struct vc4_plane_state {
+
+ /* Clipped coordinates of the plane on the display. */
+ int crtc_x, crtc_y, crtc_w, crtc_h;
+- /* Clipped size of the area scanned from in the FB. */
+- u32 src_w, src_h;
++ /* Clipped area being scanned from in the FB. */
++ u32 src_x, src_y, src_w, src_h;
++
++ enum vc4_scaling_mode x_scaling, y_scaling;
++ bool is_unity;
+
+ /* Offset to start scanning out from the start of the plane's
+ * BO.
+ */
+ u32 offset;
++
++ /* Our allocation in LBM for temporary storage during scaling. */
++ struct drm_mm_node lbm;
+ };
+
+ static inline struct vc4_plane_state *
+@@ -106,6 +118,16 @@ static const struct hvs_format *vc4_get_
+ return NULL;
+ }
+
++static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
++{
++ if (dst > src)
++ return VC4_SCALING_PPF;
++ else if (dst < src)
++ return VC4_SCALING_TPZ;
++ else
++ return VC4_SCALING_NONE;
++}
++
+ static bool plane_enabled(struct drm_plane_state *state)
+ {
+ return state->fb && state->crtc;
+@@ -122,6 +144,8 @@ static struct drm_plane_state *vc4_plane
+ if (!vc4_state)
+ return NULL;
+
++ memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
++
+ __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
+
+ if (vc4_state->dlist) {
+@@ -141,8 +165,17 @@ static struct drm_plane_state *vc4_plane
+ static void vc4_plane_destroy_state(struct drm_plane *plane,
+ struct drm_plane_state *state)
+ {
++ struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+
++ if (vc4_state->lbm.allocated) {
++ unsigned long irqflags;
++
++ spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
++ drm_mm_remove_node(&vc4_state->lbm);
++ spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
++ }
++
+ kfree(vc4_state->dlist);
+ __drm_atomic_helper_plane_destroy_state(plane, &vc4_state->base);
+ kfree(state);
+@@ -181,23 +214,60 @@ static void vc4_dlist_write(struct vc4_p
+ vc4_state->dlist[vc4_state->dlist_count++] = val;
+ }
+
++/* Returns the scl0/scl1 field based on whether the dimensions need to
++ * be up/down/non-scaled.
++ *
++ * This is a replication of a table from the spec.
++ */
++static u32 vc4_get_scl_field(struct drm_plane_state *state)
++{
++ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
++
++ switch (vc4_state->x_scaling << 2 | vc4_state->y_scaling) {
++ case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
++ return SCALER_CTL0_SCL_H_PPF_V_PPF;
++ case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
++ return SCALER_CTL0_SCL_H_TPZ_V_PPF;
++ case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
++ return SCALER_CTL0_SCL_H_PPF_V_TPZ;
++ case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
++ return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
++ case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
++ return SCALER_CTL0_SCL_H_PPF_V_NONE;
++ case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
++ return SCALER_CTL0_SCL_H_NONE_V_PPF;
++ case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
++ return SCALER_CTL0_SCL_H_NONE_V_TPZ;
++ case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
++ return SCALER_CTL0_SCL_H_TPZ_V_NONE;
++ default:
++ case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
++ /* The unity case is independently handled by
++ * SCALER_CTL0_UNITY.
++ */
++ return 0;
++ }
++}
++
+ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
+ {
++ struct drm_plane *plane = state->plane;
+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+ struct drm_framebuffer *fb = state->fb;
++ u32 subpixel_src_mask = (1 << 16) - 1;
+
+ vc4_state->offset = fb->offsets[0];
+
+- if (state->crtc_w << 16 != state->src_w ||
+- state->crtc_h << 16 != state->src_h) {
+- /* We don't support scaling yet, which involves
+- * allocating the LBM memory for scaling temporary
+- * storage, and putting filter kernels in the HVS
+- * context.
+- */
++ /* We don't support subpixel source positioning for scaling. */
++ if ((state->src_x & subpixel_src_mask) ||
++ (state->src_y & subpixel_src_mask) ||
++ (state->src_w & subpixel_src_mask) ||
++ (state->src_h & subpixel_src_mask)) {
+ return -EINVAL;
+ }
+
++ vc4_state->src_x = state->src_x >> 16;
++ vc4_state->src_y = state->src_y >> 16;
+ vc4_state->src_w = state->src_w >> 16;
+ vc4_state->src_h = state->src_h >> 16;
+
+@@ -206,6 +276,23 @@ static int vc4_plane_setup_clipping_and_
+ vc4_state->crtc_w = state->crtc_w;
+ vc4_state->crtc_h = state->crtc_h;
+
++ vc4_state->x_scaling = vc4_get_scaling_mode(vc4_state->src_w,
++ vc4_state->crtc_w);
++ vc4_state->y_scaling = vc4_get_scaling_mode(vc4_state->src_h,
++ vc4_state->crtc_h);
++ vc4_state->is_unity = (vc4_state->x_scaling == VC4_SCALING_NONE &&
++ vc4_state->y_scaling == VC4_SCALING_NONE);
++
++ /* No configuring scaling on the cursor plane, since it gets
++ non-vblank-synced updates, and scaling requires requires
++ LBM changes which have to be vblank-synced.
++ */
++ if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity)
++ return -EINVAL;
++
++ /* Clamp the on-screen start x/y to 0. The hardware doesn't
++ * support negative y, and negative x wastes bandwidth.
++ */
+ if (vc4_state->crtc_x < 0) {
+ vc4_state->offset += (drm_format_plane_cpp(fb->pixel_format,
+ 0) *
+@@ -223,6 +310,87 @@ static int vc4_plane_setup_clipping_and_
+ return 0;
+ }
+
++static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
++{
++ u32 scale, recip;
++
++ scale = (1 << 16) * src / dst;
++
++ /* The specs note that while the reciprocal would be defined
++ * as (1<<32)/scale, ~0 is close enough.
++ */
++ recip = ~0 / scale;
++
++ vc4_dlist_write(vc4_state,
++ VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
++ VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
++ vc4_dlist_write(vc4_state,
++ VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
++}
++
++static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
++{
++ u32 scale = (1 << 16) * src / dst;
++
++ vc4_dlist_write(vc4_state,
++ SCALER_PPF_AGC |
++ VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
++ VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
++}
++
++static u32 vc4_lbm_size(struct drm_plane_state *state)
++{
++ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
++ /* This is the worst case number. One of the two sizes will
++ * be used depending on the scaling configuration.
++ */
++ u32 pix_per_line = max(vc4_state->src_w, (u32)vc4_state->crtc_w);
++ u32 lbm;
++
++ if (vc4_state->is_unity)
++ return 0;
++ else if (vc4_state->y_scaling == VC4_SCALING_TPZ)
++ lbm = pix_per_line * 8;
++ else {
++ /* In special cases, this multiplier might be 12. */
++ lbm = pix_per_line * 16;
++ }
++
++ lbm = roundup(lbm, 32);
++
++ return lbm;
++}
++
++static void vc4_write_scaling_parameters(struct drm_plane_state *state)
++{
++ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
++
++ /* Ch0 H-PPF Word 0: Scaling Parameters */
++ if (vc4_state->x_scaling == VC4_SCALING_PPF) {
++ vc4_write_ppf(vc4_state,
++ vc4_state->src_w, vc4_state->crtc_w);
++ }
++
++ /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
++ if (vc4_state->y_scaling == VC4_SCALING_PPF) {
++ vc4_write_ppf(vc4_state,
++ vc4_state->src_h, vc4_state->crtc_h);
++ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
++ }
++
++ /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
++ if (vc4_state->x_scaling == VC4_SCALING_TPZ) {
++ vc4_write_tpz(vc4_state,
++ vc4_state->src_w, vc4_state->crtc_w);
++ }
++
++ /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
++ if (vc4_state->y_scaling == VC4_SCALING_TPZ) {
++ vc4_write_tpz(vc4_state,
++ vc4_state->src_h, vc4_state->crtc_h);
++ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
++ }
++}
+
+ /* Writes out a full display list for an active plane to the plane's
+ * private dlist state.
+@@ -230,22 +398,50 @@ static int vc4_plane_setup_clipping_and_
+ static int vc4_plane_mode_set(struct drm_plane *plane,
+ struct drm_plane_state *state)
+ {
++ struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+ struct drm_framebuffer *fb = state->fb;
+ struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
+ u32 ctl0_offset = vc4_state->dlist_count;
+ const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);
++ u32 scl;
++ u32 lbm_size;
++ unsigned long irqflags;
+ int ret;
+
+ ret = vc4_plane_setup_clipping_and_scaling(state);
+ if (ret)
+ return ret;
+
++ /* Allocate the LBM memory that the HVS will use for temporary
++ * storage due to our scaling/format conversion.
++ */
++ lbm_size = vc4_lbm_size(state);
++ if (lbm_size) {
++ if (!vc4_state->lbm.allocated) {
++ spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
++ ret = drm_mm_insert_node(&vc4->hvs->lbm_mm,
++ &vc4_state->lbm,
++ lbm_size, 32, 0);
++ spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
++ } else {
++ WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
++ }
++ }
++
++ if (ret)
++ return ret;
++
++ scl = vc4_get_scl_field(state);
++
++ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+- SCALER_CTL0_UNITY);
++ (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
++ VC4_SET_FIELD(scl, SCALER_CTL0_SCL0) |
++ VC4_SET_FIELD(scl, SCALER_CTL0_SCL1));
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+@@ -254,9 +450,14 @@ static int vc4_plane_mode_set(struct drm
+ VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
+ VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
+
+- /* Position Word 1: Scaled Image Dimensions.
+- * Skipped due to SCALER_CTL0_UNITY scaling.
+- */
++ /* Position Word 1: Scaled Image Dimensions. */
++ if (!vc4_state->is_unity) {
++ vc4_dlist_write(vc4_state,
++ VC4_SET_FIELD(vc4_state->crtc_w,
++ SCALER_POS1_SCL_WIDTH) |
++ VC4_SET_FIELD(vc4_state->crtc_h,
++ SCALER_POS1_SCL_HEIGHT));
++ }
+
+ /* Position Word 2: Source Image Size, Alpha Mode */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+@@ -282,6 +483,32 @@ static int vc4_plane_mode_set(struct drm
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH));
+
++ if (!vc4_state->is_unity) {
++ /* LBM Base Address. */
++ if (vc4_state->y_scaling != VC4_SCALING_NONE)
++ vc4_dlist_write(vc4_state, vc4_state->lbm.start);
++
++ vc4_write_scaling_parameters(state);
++
++ /* If any PPF setup was done, then all the kernel
++ * pointers get uploaded.
++ */
++ if (vc4_state->x_scaling == VC4_SCALING_PPF ||
++ vc4_state->y_scaling == VC4_SCALING_PPF) {
++ u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
++ SCALER_PPF_KERNEL_OFFSET);
++
++ /* HPPF plane 0 */
++ vc4_dlist_write(vc4_state, kernel);
++ /* VPPF plane 0 */
++ vc4_dlist_write(vc4_state, kernel);
++ /* HPPF plane 1 */
++ vc4_dlist_write(vc4_state, kernel);
++ /* VPPF plane 1 */
++ vc4_dlist_write(vc4_state, kernel);
++ }
++ }
++
+ vc4_state->dlist[ctl0_offset] |=
+ VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
+
+--- a/drivers/gpu/drm/vc4/vc4_regs.h
++++ b/drivers/gpu/drm/vc4/vc4_regs.h
+@@ -536,6 +536,21 @@ enum hvs_pixel_format {
+ #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
+ #define SCALER_CTL0_ORDER_SHIFT 13
+
++#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
++#define SCALER_CTL0_SCL1_SHIFT 8
++
++#define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)
++#define SCALER_CTL0_SCL0_SHIFT 5
++
++#define SCALER_CTL0_SCL_H_PPF_V_PPF 0
++#define SCALER_CTL0_SCL_H_TPZ_V_PPF 1
++#define SCALER_CTL0_SCL_H_PPF_V_TPZ 2
++#define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
++#define SCALER_CTL0_SCL_H_PPF_V_NONE 4
++#define SCALER_CTL0_SCL_H_NONE_V_PPF 5
++#define SCALER_CTL0_SCL_H_NONE_V_TPZ 6
++#define SCALER_CTL0_SCL_H_TPZ_V_NONE 7
++
+ /* Set to indicate no scaling. */
+ #define SCALER_CTL0_UNITY BIT(4)
+
+@@ -551,6 +566,12 @@ enum hvs_pixel_format {
+ #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
+ #define SCALER_POS0_START_X_SHIFT 0
+
++#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
++#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
++
++#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
++#define SCALER_POS1_SCL_WIDTH_SHIFT 0
++
+ #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
+ #define SCALER_POS2_ALPHA_MODE_SHIFT 30
+ #define SCALER_POS2_ALPHA_MODE_PIPELINE 0
+@@ -564,6 +585,31 @@ enum hvs_pixel_format {
+ #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
+ #define SCALER_POS2_WIDTH_SHIFT 0
+
++#define SCALER_TPZ0_VERT_RECALC BIT(31)
++#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
++#define SCALER_TPZ0_SCALE_SHIFT 8
++#define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
++#define SCALER_TPZ0_IPHASE_SHIFT 0
++#define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
++#define SCALER_TPZ1_RECIP_SHIFT 0
++
++/* Skips interpolating coefficients to 64 phases, so just 8 are used.
++ * Required for nearest neighbor.
++ */
++#define SCALER_PPF_NOINTERP BIT(31)
++/* Replaes the highest valued coefficient with one that makes all 4
++ * sum to unity.
++ */
++#define SCALER_PPF_AGC BIT(30)
++#define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
++#define SCALER_PPF_SCALE_SHIFT 8
++#define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
++#define SCALER_PPF_IPHASE_SHIFT 0
++
++#define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
++#define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
++#define SCALER_PPF_KERNEL_UNCACHED BIT(31)
++
+ #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
+ #define SCALER_SRC_PITCH_SHIFT 0
+
--- /dev/null
+From 59b40e05378ba51d3e5355f8860fca1341edf0c0 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Wed, 30 Dec 2015 12:25:44 -0800
+Subject: [PATCH 286/304] drm/vc4: Add support for YUV planes.
+
+This supports 420 and 422 subsampling with 2 or 3 planes, tested with
+modetest. It doesn't set up chroma subsampling position (which it
+appears KMS doesn't deal with yet).
+
+The LBM memory is overallocated in many cases, but apparently the docs
+aren't quite correct and I'll probably need to look at the hardware
+source to really figure it out.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit fc04023fafecf19ebd09278d8d67dc5ed1f68b46)
+---
+ drivers/gpu/drm/vc4/vc4_plane.c | 256 +++++++++++++++++++++++++++++++---------
+ drivers/gpu/drm/vc4/vc4_regs.h | 56 ++++++++-
+ 2 files changed, 253 insertions(+), 59 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_plane.c
++++ b/drivers/gpu/drm/vc4/vc4_plane.c
+@@ -54,15 +54,19 @@ struct vc4_plane_state {
+ /* Clipped coordinates of the plane on the display. */
+ int crtc_x, crtc_y, crtc_w, crtc_h;
+ /* Clipped area being scanned from in the FB. */
+- u32 src_x, src_y, src_w, src_h;
++ u32 src_x, src_y;
+
+- enum vc4_scaling_mode x_scaling, y_scaling;
++ u32 src_w[2], src_h[2];
++
++ /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
++ enum vc4_scaling_mode x_scaling[2], y_scaling[2];
+ bool is_unity;
++ bool is_yuv;
+
+ /* Offset to start scanning out from the start of the plane's
+ * BO.
+ */
+- u32 offset;
++ u32 offsets[3];
+
+ /* Our allocation in LBM for temporary storage during scaling. */
+ struct drm_mm_node lbm;
+@@ -79,6 +83,7 @@ static const struct hvs_format {
+ u32 hvs; /* HVS_FORMAT_* */
+ u32 pixel_order;
+ bool has_alpha;
++ bool flip_cbcr;
+ } hvs_formats[] = {
+ {
+ .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+@@ -104,6 +109,32 @@ static const struct hvs_format {
+ .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false,
+ },
++ {
++ .drm = DRM_FORMAT_YUV422,
++ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
++ },
++ {
++ .drm = DRM_FORMAT_YVU422,
++ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
++ .flip_cbcr = true,
++ },
++ {
++ .drm = DRM_FORMAT_YUV420,
++ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
++ },
++ {
++ .drm = DRM_FORMAT_YVU420,
++ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
++ .flip_cbcr = true,
++ },
++ {
++ .drm = DRM_FORMAT_NV12,
++ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
++ },
++ {
++ .drm = DRM_FORMAT_NV16,
++ .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
++ },
+ };
+
+ static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
+@@ -219,11 +250,11 @@ static void vc4_dlist_write(struct vc4_p
+ *
+ * This is a replication of a table from the spec.
+ */
+-static u32 vc4_get_scl_field(struct drm_plane_state *state)
++static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
+ {
+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+
+- switch (vc4_state->x_scaling << 2 | vc4_state->y_scaling) {
++ switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
+ case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
+ return SCALER_CTL0_SCL_H_PPF_V_PPF;
+ case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
+@@ -254,9 +285,16 @@ static int vc4_plane_setup_clipping_and_
+ struct drm_plane *plane = state->plane;
+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+ struct drm_framebuffer *fb = state->fb;
++ struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
+ u32 subpixel_src_mask = (1 << 16) - 1;
++ u32 format = fb->pixel_format;
++ int num_planes = drm_format_num_planes(format);
++ u32 h_subsample = 1;
++ u32 v_subsample = 1;
++ int i;
+
+- vc4_state->offset = fb->offsets[0];
++ for (i = 0; i < num_planes; i++)
++ vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
+
+ /* We don't support subpixel source positioning for scaling. */
+ if ((state->src_x & subpixel_src_mask) ||
+@@ -268,20 +306,48 @@ static int vc4_plane_setup_clipping_and_
+
+ vc4_state->src_x = state->src_x >> 16;
+ vc4_state->src_y = state->src_y >> 16;
+- vc4_state->src_w = state->src_w >> 16;
+- vc4_state->src_h = state->src_h >> 16;
++ vc4_state->src_w[0] = state->src_w >> 16;
++ vc4_state->src_h[0] = state->src_h >> 16;
+
+ vc4_state->crtc_x = state->crtc_x;
+ vc4_state->crtc_y = state->crtc_y;
+ vc4_state->crtc_w = state->crtc_w;
+ vc4_state->crtc_h = state->crtc_h;
+
+- vc4_state->x_scaling = vc4_get_scaling_mode(vc4_state->src_w,
+- vc4_state->crtc_w);
+- vc4_state->y_scaling = vc4_get_scaling_mode(vc4_state->src_h,
+- vc4_state->crtc_h);
+- vc4_state->is_unity = (vc4_state->x_scaling == VC4_SCALING_NONE &&
+- vc4_state->y_scaling == VC4_SCALING_NONE);
++ vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
++ vc4_state->crtc_w);
++ vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
++ vc4_state->crtc_h);
++
++ if (num_planes > 1) {
++ vc4_state->is_yuv = true;
++
++ h_subsample = drm_format_horz_chroma_subsampling(format);
++ v_subsample = drm_format_vert_chroma_subsampling(format);
++ vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
++ vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
++
++ vc4_state->x_scaling[1] =
++ vc4_get_scaling_mode(vc4_state->src_w[1],
++ vc4_state->crtc_w);
++ vc4_state->y_scaling[1] =
++ vc4_get_scaling_mode(vc4_state->src_h[1],
++ vc4_state->crtc_h);
++
++ /* YUV conversion requires that scaling be enabled,
++ * even on a plane that's otherwise 1:1. Choose TPZ
++ * for simplicity.
++ */
++ if (vc4_state->x_scaling[0] == VC4_SCALING_NONE)
++ vc4_state->x_scaling[0] = VC4_SCALING_TPZ;
++ if (vc4_state->y_scaling[0] == VC4_SCALING_NONE)
++ vc4_state->y_scaling[0] = VC4_SCALING_TPZ;
++ }
++
++ vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
++ vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
++ vc4_state->x_scaling[1] == VC4_SCALING_NONE &&
++ vc4_state->y_scaling[1] == VC4_SCALING_NONE);
+
+ /* No configuring scaling on the cursor plane, since it gets
+ non-vblank-synced updates, and scaling requires requires
+@@ -294,16 +360,27 @@ static int vc4_plane_setup_clipping_and_
+ * support negative y, and negative x wastes bandwidth.
+ */
+ if (vc4_state->crtc_x < 0) {
+- vc4_state->offset += (drm_format_plane_cpp(fb->pixel_format,
+- 0) *
+- -vc4_state->crtc_x);
+- vc4_state->src_w += vc4_state->crtc_x;
++ for (i = 0; i < num_planes; i++) {
++ u32 cpp = drm_format_plane_cpp(fb->pixel_format, i);
++ u32 subs = ((i == 0) ? 1 : h_subsample);
++
++ vc4_state->offsets[i] += (cpp *
++ (-vc4_state->crtc_x) / subs);
++ }
++ vc4_state->src_w[0] += vc4_state->crtc_x;
++ vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample;
+ vc4_state->crtc_x = 0;
+ }
+
+ if (vc4_state->crtc_y < 0) {
+- vc4_state->offset += fb->pitches[0] * -vc4_state->crtc_y;
+- vc4_state->src_h += vc4_state->crtc_y;
++ for (i = 0; i < num_planes; i++) {
++ u32 subs = ((i == 0) ? 1 : v_subsample);
++
++ vc4_state->offsets[i] += (fb->pitches[i] *
++ (-vc4_state->crtc_y) / subs);
++ }
++ vc4_state->src_h[0] += vc4_state->crtc_y;
++ vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample;
+ vc4_state->crtc_y = 0;
+ }
+
+@@ -344,15 +421,23 @@ static u32 vc4_lbm_size(struct drm_plane
+ /* This is the worst case number. One of the two sizes will
+ * be used depending on the scaling configuration.
+ */
+- u32 pix_per_line = max(vc4_state->src_w, (u32)vc4_state->crtc_w);
++ u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
+ u32 lbm;
+
+- if (vc4_state->is_unity)
+- return 0;
+- else if (vc4_state->y_scaling == VC4_SCALING_TPZ)
+- lbm = pix_per_line * 8;
+- else {
+- /* In special cases, this multiplier might be 12. */
++ if (!vc4_state->is_yuv) {
++ if (vc4_state->is_unity)
++ return 0;
++ else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
++ lbm = pix_per_line * 8;
++ else {
++ /* In special cases, this multiplier might be 12. */
++ lbm = pix_per_line * 16;
++ }
++ } else {
++ /* There are cases for this going down to a multiplier
++ * of 2, but according to the firmware source, the
++ * table in the docs is somewhat wrong.
++ */
+ lbm = pix_per_line * 16;
+ }
+
+@@ -361,33 +446,34 @@ static u32 vc4_lbm_size(struct drm_plane
+ return lbm;
+ }
+
+-static void vc4_write_scaling_parameters(struct drm_plane_state *state)
++static void vc4_write_scaling_parameters(struct drm_plane_state *state,
++ int channel)
+ {
+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+
+ /* Ch0 H-PPF Word 0: Scaling Parameters */
+- if (vc4_state->x_scaling == VC4_SCALING_PPF) {
++ if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
+ vc4_write_ppf(vc4_state,
+- vc4_state->src_w, vc4_state->crtc_w);
++ vc4_state->src_w[channel], vc4_state->crtc_w);
+ }
+
+ /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
+- if (vc4_state->y_scaling == VC4_SCALING_PPF) {
++ if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
+ vc4_write_ppf(vc4_state,
+- vc4_state->src_h, vc4_state->crtc_h);
++ vc4_state->src_h[channel], vc4_state->crtc_h);
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ }
+
+ /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
+- if (vc4_state->x_scaling == VC4_SCALING_TPZ) {
++ if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
+ vc4_write_tpz(vc4_state,
+- vc4_state->src_w, vc4_state->crtc_w);
++ vc4_state->src_w[channel], vc4_state->crtc_w);
+ }
+
+ /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
+- if (vc4_state->y_scaling == VC4_SCALING_TPZ) {
++ if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
+ vc4_write_tpz(vc4_state,
+- vc4_state->src_h, vc4_state->crtc_h);
++ vc4_state->src_h[channel], vc4_state->crtc_h);
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ }
+ }
+@@ -401,13 +487,13 @@ static int vc4_plane_mode_set(struct drm
+ struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
+ struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
+ struct drm_framebuffer *fb = state->fb;
+- struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
+ u32 ctl0_offset = vc4_state->dlist_count;
+ const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format);
+- u32 scl;
++ int num_planes = drm_format_num_planes(format->drm);
++ u32 scl0, scl1;
+ u32 lbm_size;
+ unsigned long irqflags;
+- int ret;
++ int ret, i;
+
+ ret = vc4_plane_setup_clipping_and_scaling(state);
+ if (ret)
+@@ -432,7 +518,19 @@ static int vc4_plane_mode_set(struct drm
+ if (ret)
+ return ret;
+
+- scl = vc4_get_scl_field(state);
++ /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB
++ * and 4:4:4, scl1 should be set to scl0 so both channels of
++ * the scaler do the same thing. For YUV, the Y plane needs
++ * to be put in channel 1 and Cb/Cr in channel 0, so we swap
++ * the scl fields here.
++ */
++ if (num_planes == 1) {
++ scl0 = vc4_get_scl_field(state, 1);
++ scl1 = scl0;
++ } else {
++ scl0 = vc4_get_scl_field(state, 1);
++ scl1 = vc4_get_scl_field(state, 0);
++ }
+
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+@@ -440,8 +538,8 @@ static int vc4_plane_mode_set(struct drm
+ (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
+- VC4_SET_FIELD(scl, SCALER_CTL0_SCL0) |
+- VC4_SET_FIELD(scl, SCALER_CTL0_SCL1));
++ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
++ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+@@ -466,35 +564,68 @@ static int vc4_plane_mode_set(struct drm
+ SCALER_POS2_ALPHA_MODE_PIPELINE :
+ SCALER_POS2_ALPHA_MODE_FIXED,
+ SCALER_POS2_ALPHA_MODE) |
+- VC4_SET_FIELD(vc4_state->src_w, SCALER_POS2_WIDTH) |
+- VC4_SET_FIELD(vc4_state->src_h, SCALER_POS2_HEIGHT));
++ VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
++ VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+
+- /* Pointer Word 0: RGB / Y Pointer */
++
++ /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
++ *
++ * The pointers may be any byte address.
++ */
+ vc4_state->ptr0_offset = vc4_state->dlist_count;
+- vc4_dlist_write(vc4_state, bo->paddr + vc4_state->offset);
++ if (!format->flip_cbcr) {
++ for (i = 0; i < num_planes; i++)
++ vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
++ } else {
++ WARN_ON_ONCE(num_planes != 3);
++ vc4_dlist_write(vc4_state, vc4_state->offsets[0]);
++ vc4_dlist_write(vc4_state, vc4_state->offsets[2]);
++ vc4_dlist_write(vc4_state, vc4_state->offsets[1]);
++ }
+
+- /* Pointer Context Word 0: Written by the HVS */
+- vc4_dlist_write(vc4_state, 0xc0c0c0c0);
++ /* Pointer Context Word 0/1/2: Written by the HVS */
++ for (i = 0; i < num_planes; i++)
++ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+
+- /* Pitch word 0: Pointer 0 Pitch */
+- vc4_dlist_write(vc4_state,
+- VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH));
++ /* Pitch word 0/1/2 */
++ for (i = 0; i < num_planes; i++) {
++ vc4_dlist_write(vc4_state,
++ VC4_SET_FIELD(fb->pitches[i], SCALER_SRC_PITCH));
++ }
++
++ /* Colorspace conversion words */
++ if (vc4_state->is_yuv) {
++ vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
++ vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
++ vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
++ }
+
+ if (!vc4_state->is_unity) {
+ /* LBM Base Address. */
+- if (vc4_state->y_scaling != VC4_SCALING_NONE)
++ if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
++ vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
+ vc4_dlist_write(vc4_state, vc4_state->lbm.start);
++ }
+
+- vc4_write_scaling_parameters(state);
++ if (num_planes > 1) {
++ /* Emit Cb/Cr as channel 0 and Y as channel
++ * 1. This matches how we set up scl0/scl1
++ * above.
++ */
++ vc4_write_scaling_parameters(state, 1);
++ }
++ vc4_write_scaling_parameters(state, 0);
+
+ /* If any PPF setup was done, then all the kernel
+ * pointers get uploaded.
+ */
+- if (vc4_state->x_scaling == VC4_SCALING_PPF ||
+- vc4_state->y_scaling == VC4_SCALING_PPF) {
++ if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
++ vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
++ vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
++ vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
+ u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
+ SCALER_PPF_KERNEL_OFFSET);
+
+@@ -698,6 +829,7 @@ struct drm_plane *vc4_plane_init(struct
+ struct drm_plane *plane = NULL;
+ struct vc4_plane *vc4_plane;
+ u32 formats[ARRAY_SIZE(hvs_formats)];
++ u32 num_formats = 0;
+ int ret = 0;
+ unsigned i;
+
+@@ -708,12 +840,20 @@ struct drm_plane *vc4_plane_init(struct
+ goto fail;
+ }
+
+- for (i = 0; i < ARRAY_SIZE(hvs_formats); i++)
+- formats[i] = hvs_formats[i].drm;
++ for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
++ /* Don't allow YUV in cursor planes, since that means
++ * tuning on the scaler, which we don't allow for the
++ * cursor.
++ */
++ if (type != DRM_PLANE_TYPE_CURSOR ||
++ hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) {
++ formats[num_formats++] = hvs_formats[i].drm;
++ }
++ }
+ plane = &vc4_plane->base;
+ ret = drm_universal_plane_init(dev, plane, 0xff,
+ &vc4_plane_funcs,
+- formats, ARRAY_SIZE(formats),
++ formats, num_formats,
+ type);
+
+ drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
+--- a/drivers/gpu/drm/vc4/vc4_regs.h
++++ b/drivers/gpu/drm/vc4/vc4_regs.h
+@@ -503,7 +503,12 @@ enum hvs_pixel_format {
+ HVS_PIXEL_FORMAT_RGB888 = 5,
+ HVS_PIXEL_FORMAT_RGBA6666 = 6,
+ /* 32bpp */
+- HVS_PIXEL_FORMAT_RGBA8888 = 7
++ HVS_PIXEL_FORMAT_RGBA8888 = 7,
++
++ HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
++ HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
++ HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
++ HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
+ };
+
+ /* Note: the LSB is the rightmost character shown. Only valid for
+@@ -585,6 +590,55 @@ enum hvs_pixel_format {
+ #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
+ #define SCALER_POS2_WIDTH_SHIFT 0
+
++/* Color Space Conversion words. Some values are S2.8 signed
++ * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
++ * 0x2: 2, 0x3: -1}
++ */
++/* bottom 8 bits of S2.8 contribution of Cr to Blue */
++#define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
++#define SCALER_CSC0_COEF_CR_BLU_SHIFT 24
++/* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */
++#define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)
++#define SCALER_CSC0_COEF_YY_OFS_SHIFT 16
++/* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
++#define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
++#define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
++/* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
++#define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)
++#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
++#define SCALER_CSC0_ITR_R_601_5 0x00f00000
++#define SCALER_CSC0_ITR_R_709_3 0x00f00000
++#define SCALER_CSC0_JPEG_JFIF 0x00000000
++
++/* S2.8 contribution of Cb to Green */
++#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
++#define SCALER_CSC1_COEF_CB_GRN_SHIFT 22
++/* S2.8 contribution of Cr to Green */
++#define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)
++#define SCALER_CSC1_COEF_CR_GRN_SHIFT 12
++/* S2.8 contribution of Y to all of RGB */
++#define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)
++#define SCALER_CSC1_COEF_YY_ALL_SHIFT 2
++/* top 2 bits of S2.8 contribution of Cr to Blue */
++#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
++#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
++#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
++#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
++#define SCALER_CSC1_JPEG_JFIF 0xea34a400
++
++/* S2.8 contribution of Cb to Red */
++#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
++#define SCALER_CSC2_COEF_CB_RED_SHIFT 20
++/* S2.8 contribution of Cr to Red */
++#define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)
++#define SCALER_CSC2_COEF_CR_RED_SHIFT 10
++/* S2.8 contribution of Cb to Blue */
++#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
++#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
++#define SCALER_CSC2_ITR_R_601_5 0x00066204
++#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
++#define SCALER_CSC2_JPEG_JFIF 0x000599c5
++
+ #define SCALER_TPZ0_VERT_RECALC BIT(31)
+ #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
+ #define SCALER_TPZ0_SCALE_SHIFT 8
--- /dev/null
+From 6fde872f91f4ff8dcf1b2c2017c04e4f1dee07f7 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 8 Feb 2016 11:19:14 -0800
+Subject: [PATCH 287/304] drm/vc4: Fix spurious GPU resets due to BO reuse.
+
+We were tracking the "where are the head pointers pointing" globally,
+so if another job reused the same BOs and execution was at the same
+point as last time we checked, we'd stop and trigger a reset even
+though the GPU had made progress.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit c4ce60dc30912df09b2438f1e5594eae1ef64d1e)
+---
+ drivers/gpu/drm/vc4/vc4_drv.h | 6 +++++-
+ drivers/gpu/drm/vc4/vc4_gem.c | 19 ++++++++++++++-----
+ 2 files changed, 19 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_drv.h
++++ b/drivers/gpu/drm/vc4/vc4_drv.h
+@@ -93,7 +93,6 @@ struct vc4_dev {
+ struct work_struct overflow_mem_work;
+
+ struct {
+- uint32_t last_ct0ca, last_ct1ca;
+ struct timer_list timer;
+ struct work_struct reset_work;
+ } hangcheck;
+@@ -203,6 +202,11 @@ struct vc4_exec_info {
+ /* Sequence number for this bin/render job. */
+ uint64_t seqno;
+
++ /* Last current addresses the hardware was processing when the
++ * hangcheck timer checked on us.
++ */
++ uint32_t last_ct0ca, last_ct1ca;
++
+ /* Kernel-space copy of the ioctl arguments */
+ struct drm_vc4_submit_cl *args;
+
+--- a/drivers/gpu/drm/vc4/vc4_gem.c
++++ b/drivers/gpu/drm/vc4/vc4_gem.c
+@@ -271,10 +271,17 @@ vc4_hangcheck_elapsed(unsigned long data
+ struct drm_device *dev = (struct drm_device *)data;
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+ uint32_t ct0ca, ct1ca;
++ unsigned long irqflags;
++ struct vc4_exec_info *exec;
++
++ spin_lock_irqsave(&vc4->job_lock, irqflags);
++ exec = vc4_first_job(vc4);
+
+ /* If idle, we can stop watching for hangs. */
+- if (list_empty(&vc4->job_list))
++ if (!exec) {
++ spin_unlock_irqrestore(&vc4->job_lock, irqflags);
+ return;
++ }
+
+ ct0ca = V3D_READ(V3D_CTNCA(0));
+ ct1ca = V3D_READ(V3D_CTNCA(1));
+@@ -282,14 +289,16 @@ vc4_hangcheck_elapsed(unsigned long data
+ /* If we've made any progress in execution, rearm the timer
+ * and wait.
+ */
+- if (ct0ca != vc4->hangcheck.last_ct0ca ||
+- ct1ca != vc4->hangcheck.last_ct1ca) {
+- vc4->hangcheck.last_ct0ca = ct0ca;
+- vc4->hangcheck.last_ct1ca = ct1ca;
++ if (ct0ca != exec->last_ct0ca || ct1ca != exec->last_ct1ca) {
++ exec->last_ct0ca = ct0ca;
++ exec->last_ct1ca = ct1ca;
++ spin_unlock_irqrestore(&vc4->job_lock, irqflags);
+ vc4_queue_hangcheck(dev);
+ return;
+ }
+
++ spin_unlock_irqrestore(&vc4->job_lock, irqflags);
++
+ /* We've gone too long with no progress, reset. This has to
+ * be done from a work struct, since resetting can sleep and
+ * this timer hook isn't allowed to.
--- /dev/null
+From af6fb397532633e85bb101801d8156b2263aa54f Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Fri, 5 Feb 2016 15:06:15 -0800
+Subject: [PATCH 288/304] drm/vc4: Fix a framebuffer reference leak on async
+ flip interrupt.
+
+We'd need X to queue up an async pageflip while another is
+outstanding, and then take a SIGIO. I think X actually avoids sending
+out the next pageflip while one's already queued, but I'm not sure.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 48627eb8dc55c60d35794105f6f79fb627347dbd)
+---
+ drivers/gpu/drm/vc4/vc4_crtc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/vc4/vc4_crtc.c
++++ b/drivers/gpu/drm/vc4/vc4_crtc.c
+@@ -527,6 +527,7 @@ static int vc4_async_page_flip(struct dr
+ /* Make sure all other async modesetes have landed. */
+ ret = down_interruptible(&vc4->async_modeset);
+ if (ret) {
++ drm_framebuffer_unreference(fb);
+ kfree(flip_state);
+ return ret;
+ }
--- /dev/null
+From e25771aa6a4b2b701f3280956d97de4682c54231 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Fri, 12 Feb 2016 14:15:14 -0800
+Subject: [PATCH 289/304] drm/vc4: Bring HDMI up from power off if necessary.
+
+If the firmware hadn't brought up HDMI for us, we need to do its
+power-on reset sequence (reset HD and and clear its STANDBY bits,
+reset HDMI, and leave the PHY disabled).
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 851479ad5927b7b1aa141ca9dedb897a7bce2b1d)
+---
+ drivers/gpu/drm/vc4/vc4_hdmi.c | 29 ++++++++++++++++++++++++++++-
+ drivers/gpu/drm/vc4/vc4_regs.h | 2 ++
+ 2 files changed, 30 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
++++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
+@@ -497,6 +497,16 @@ static int vc4_hdmi_bind(struct device *
+ goto err_put_i2c;
+ }
+
++ /* This is the rate that is set by the firmware. The number
++ * needs to be a bit higher than the pixel clock rate
++ * (generally 148.5Mhz).
++ */
++ ret = clk_set_rate(hdmi->hsm_clock, 163682864);
++ if (ret) {
++ DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
++ goto err_unprepare_pix;
++ }
++
+ ret = clk_prepare_enable(hdmi->hsm_clock);
+ if (ret) {
+ DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
+@@ -518,7 +528,24 @@ static int vc4_hdmi_bind(struct device *
+ vc4->hdmi = hdmi;
+
+ /* HDMI core must be enabled. */
+- WARN_ON_ONCE((HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE) == 0);
++ if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
++ HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
++ udelay(1);
++ HD_WRITE(VC4_HD_M_CTL, 0);
++
++ HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
++
++ HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
++ VC4_HDMI_SW_RESET_HDMI |
++ VC4_HDMI_SW_RESET_FORMAT_DETECT);
++
++ HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
++
++ /* PHY should be in reset, like
++ * vc4_hdmi_encoder_disable() does.
++ */
++ HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
++ }
+
+ drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
+ DRM_MODE_ENCODER_TMDS);
+--- a/drivers/gpu/drm/vc4/vc4_regs.h
++++ b/drivers/gpu/drm/vc4/vc4_regs.h
+@@ -456,6 +456,8 @@
+ #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
+
+ #define VC4_HD_M_CTL 0x00c
++# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
++# define VC4_HD_M_RAM_STANDBY (3 << 4)
+ # define VC4_HD_M_SW_RST BIT(2)
+ # define VC4_HD_M_ENABLE BIT(0)
+
--- /dev/null
+From 816b426c27ea90f113f83a7a767e03aa78fbcc03 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Fri, 12 Feb 2016 15:16:56 -0800
+Subject: [PATCH 290/304] drm/vc4: Add another reg to HDMI debug dumping.
+
+This is also involved in the HDMI setup sequence so it's nice to see
+it.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 936f1a53f32148cc6164fad7c9a26ebf144e5ffb)
+---
+ drivers/gpu/drm/vc4/vc4_hdmi.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
++++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
+@@ -95,6 +95,7 @@ static const struct {
+ HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
+ HDMI_REG(VC4_HDMI_HOTPLUG_INT),
+ HDMI_REG(VC4_HDMI_HOTPLUG),
++ HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
+ HDMI_REG(VC4_HDMI_HORZA),
+ HDMI_REG(VC4_HDMI_HORZB),
+ HDMI_REG(VC4_HDMI_FIFO_CTL),
--- /dev/null
+From e3f14344d3d427d0b9cdbf4e3039d88320836471 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 15 Feb 2016 17:06:02 -0800
+Subject: [PATCH 291/304] drm/vc4: Fix the name of the VSYNCD_EVEN register.
+
+It's used for delaying vsync in interlaced mode.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit c31806fbdda910d337b60896040afa708bdfa2bd)
+---
+ drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
+ drivers/gpu/drm/vc4/vc4_regs.h | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_crtc.c
++++ b/drivers/gpu/drm/vc4/vc4_crtc.c
+@@ -88,7 +88,7 @@ static const struct {
+ } crtc_regs[] = {
+ CRTC_REG(PV_CONTROL),
+ CRTC_REG(PV_V_CONTROL),
+- CRTC_REG(PV_VSYNCD),
++ CRTC_REG(PV_VSYNCD_EVEN),
+ CRTC_REG(PV_HORZA),
+ CRTC_REG(PV_HORZB),
+ CRTC_REG(PV_VERTA),
+--- a/drivers/gpu/drm/vc4/vc4_regs.h
++++ b/drivers/gpu/drm/vc4/vc4_regs.h
+@@ -187,7 +187,7 @@
+ # define PV_VCONTROL_CONTINUOUS BIT(1)
+ # define PV_VCONTROL_VIDEN BIT(0)
+
+-#define PV_VSYNCD 0x08
++#define PV_VSYNCD_EVEN 0x08
+
+ #define PV_HORZA 0x0c
+ # define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
--- /dev/null
+From a0d015caa8ddfd37ae8cbfc7aec1d614b5ad3b78 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 15 Feb 2016 17:31:41 -0800
+Subject: [PATCH 292/304] drm/vc4: Fix setting of vertical timings in the CRTC.
+
+It looks like when I went to add the interlaced bits, I just took the
+existing PV_VERT* block and indented it, instead of copy and pasting
+it first. Without this, changing resolution never worked.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit a7c5047d1ce178dd2b1fa577fc8909ad663d56d5)
+---
+ drivers/gpu/drm/vc4/vc4_crtc.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/gpu/drm/vc4/vc4_crtc.c
++++ b/drivers/gpu/drm/vc4/vc4_crtc.c
+@@ -217,6 +217,16 @@ static void vc4_crtc_mode_set_nofb(struc
+ PV_HORZB_HFP) |
+ VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
+
++ CRTC_WRITE(PV_VERTA,
++ VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
++ PV_VERTA_VBP) |
++ VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
++ PV_VERTA_VSYNC));
++ CRTC_WRITE(PV_VERTB,
++ VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
++ PV_VERTB_VFP) |
++ VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
++
+ if (interlace) {
+ CRTC_WRITE(PV_VERTA_EVEN,
+ VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
--- /dev/null
+From 072c90e010990be7841b88b268b9fb29806088e0 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 16 Feb 2016 10:24:08 -0800
+Subject: [PATCH 293/304] drm/vc4: Initialize scaler DISPBKGND on modeset.
+
+We weren't updating the interlaced bit, so we'd scan out incorrectly
+if the firmware had brought up the TV encoder and we were switching to
+HDMI.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 6a609209865247cc748e90158c99f374f79b494c)
+---
+ drivers/gpu/drm/vc4/vc4_crtc.c | 6 ++++++
+ drivers/gpu/drm/vc4/vc4_regs.h | 14 ++++++++++++++
+ 2 files changed, 20 insertions(+)
+
+--- a/drivers/gpu/drm/vc4/vc4_crtc.c
++++ b/drivers/gpu/drm/vc4/vc4_crtc.c
+@@ -188,6 +188,8 @@ static int vc4_get_clock_select(struct d
+
+ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
+ {
++ struct drm_device *dev = crtc->dev;
++ struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct drm_crtc_state *state = crtc->state;
+ struct drm_display_mode *mode = &state->adjusted_mode;
+@@ -256,6 +258,10 @@ static void vc4_crtc_mode_set_nofb(struc
+ PV_CONTROL_FIFO_CLR |
+ PV_CONTROL_EN);
+
++ HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
++ SCALER_DISPBKGND_AUTOHS |
++ (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
++
+ if (debug_dump_regs) {
+ DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
+ vc4_crtc_dump_regs(vc4_crtc);
+--- a/drivers/gpu/drm/vc4/vc4_regs.h
++++ b/drivers/gpu/drm/vc4/vc4_regs.h
+@@ -350,6 +350,17 @@
+ # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
+
+ #define SCALER_DISPBKGND0 0x00000044
++# define SCALER_DISPBKGND_AUTOHS BIT(31)
++# define SCALER_DISPBKGND_INTERLACE BIT(30)
++# define SCALER_DISPBKGND_GAMMA BIT(29)
++# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
++# define SCALER_DISPBKGND_TESTMODE_SHIFT 25
++/* Enables filling the scaler line with the RGB value in the low 24
++ * bits before compositing. Costs cycles, so should be skipped if
++ * opaque display planes will cover everything.
++ */
++# define SCALER_DISPBKGND_FILL BIT(24)
++
+ #define SCALER_DISPSTAT0 0x00000048
+ #define SCALER_DISPBASE0 0x0000004c
+ # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
+@@ -362,6 +373,9 @@
+ # define SCALER_DISPSTATX_EMPTY BIT(28)
+ #define SCALER_DISPCTRL1 0x00000050
+ #define SCALER_DISPBKGND1 0x00000054
++#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
++ (x) * (SCALER_DISPBKGND1 - \
++ SCALER_DISPBKGND0))
+ #define SCALER_DISPSTAT1 0x00000058
+ #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
+ (x) * (SCALER_DISPSTAT1 - \
--- /dev/null
+From a2c21b04f340f594c16f9c7235ec7b7f78a96a1f Mon Sep 17 00:00:00 2001
+From: Varad Gautam <varadgautam@gmail.com>
+Date: Wed, 17 Feb 2016 19:08:21 +0530
+Subject: [PATCH 294/304] drm/vc4: improve throughput by pipelining binning and
+ rendering jobs
+
+The hardware provides us with separate threads for binning and
+rendering, and the existing model waits for them both to complete
+before submitting the next job.
+
+Splitting the binning and rendering submissions reduces idle time and
+gives us approx 20-30% speedup with some x11perf tests such as -line10
+and -tilerect1. Improves openarena performance by 1.01897% +/-
+0.247857% (n=16).
+
+Thanks to anholt for suggesting this.
+
+v2: Rebase on the spurious resets fix (change by anholt).
+
+Signed-off-by: Varad Gautam <varadgautam@gmail.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit ca26d28bbaa39f31d5e7e4812603b015c8d54207)
+---
+ drivers/gpu/drm/vc4/vc4_drv.h | 37 +++++++++----
+ drivers/gpu/drm/vc4/vc4_gem.c | 123 ++++++++++++++++++++++++++++++------------
+ drivers/gpu/drm/vc4/vc4_irq.c | 58 ++++++++++++++++----
+ 3 files changed, 166 insertions(+), 52 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_drv.h
++++ b/drivers/gpu/drm/vc4/vc4_drv.h
+@@ -53,7 +53,7 @@ struct vc4_dev {
+ /* Protects bo_cache and the BO stats. */
+ struct mutex bo_lock;
+
+- /* Sequence number for the last job queued in job_list.
++ /* Sequence number for the last job queued in bin_job_list.
+ * Starts at 0 (no jobs emitted).
+ */
+ uint64_t emit_seqno;
+@@ -63,11 +63,19 @@ struct vc4_dev {
+ */
+ uint64_t finished_seqno;
+
+- /* List of all struct vc4_exec_info for jobs to be executed.
+- * The first job in the list is the one currently programmed
+- * into ct0ca/ct1ca for execution.
++ /* List of all struct vc4_exec_info for jobs to be executed in
++ * the binner. The first job in the list is the one currently
++ * programmed into ct0ca for execution.
++ */
++ struct list_head bin_job_list;
++
++ /* List of all struct vc4_exec_info for jobs that have
++ * completed binning and are ready for rendering. The first
++ * job in the list is the one currently programmed into ct1ca
++ * for execution.
+ */
+- struct list_head job_list;
++ struct list_head render_job_list;
++
+ /* List of the finished vc4_exec_infos waiting to be freed by
+ * job_done_work.
+ */
+@@ -291,11 +299,20 @@ struct vc4_exec_info {
+ };
+
+ static inline struct vc4_exec_info *
+-vc4_first_job(struct vc4_dev *vc4)
++vc4_first_bin_job(struct vc4_dev *vc4)
++{
++ if (list_empty(&vc4->bin_job_list))
++ return NULL;
++ return list_first_entry(&vc4->bin_job_list, struct vc4_exec_info, head);
++}
++
++static inline struct vc4_exec_info *
++vc4_first_render_job(struct vc4_dev *vc4)
+ {
+- if (list_empty(&vc4->job_list))
++ if (list_empty(&vc4->render_job_list))
+ return NULL;
+- return list_first_entry(&vc4->job_list, struct vc4_exec_info, head);
++ return list_first_entry(&vc4->render_job_list,
++ struct vc4_exec_info, head);
+ }
+
+ /**
+@@ -410,7 +427,9 @@ int vc4_wait_seqno_ioctl(struct drm_devi
+ struct drm_file *file_priv);
+ int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+-void vc4_submit_next_job(struct drm_device *dev);
++void vc4_submit_next_bin_job(struct drm_device *dev);
++void vc4_submit_next_render_job(struct drm_device *dev);
++void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
+ int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
+ uint64_t timeout_ns, bool interruptible);
+ void vc4_job_handle_completed(struct vc4_dev *vc4);
+--- a/drivers/gpu/drm/vc4/vc4_gem.c
++++ b/drivers/gpu/drm/vc4/vc4_gem.c
+@@ -154,10 +154,10 @@ vc4_save_hang_state(struct drm_device *d
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct drm_vc4_get_hang_state *state;
+ struct vc4_hang_state *kernel_state;
+- struct vc4_exec_info *exec;
++ struct vc4_exec_info *exec[2];
+ struct vc4_bo *bo;
+ unsigned long irqflags;
+- unsigned int i, unref_list_count;
++ unsigned int i, j, unref_list_count, prev_idx;
+
+ kernel_state = kcalloc(1, sizeof(*kernel_state), GFP_KERNEL);
+ if (!kernel_state)
+@@ -166,37 +166,55 @@ vc4_save_hang_state(struct drm_device *d
+ state = &kernel_state->user_state;
+
+ spin_lock_irqsave(&vc4->job_lock, irqflags);
+- exec = vc4_first_job(vc4);
+- if (!exec) {
++ exec[0] = vc4_first_bin_job(vc4);
++ exec[1] = vc4_first_render_job(vc4);
++ if (!exec[0] && !exec[1]) {
+ spin_unlock_irqrestore(&vc4->job_lock, irqflags);
+ return;
+ }
+
+- unref_list_count = 0;
+- list_for_each_entry(bo, &exec->unref_list, unref_head)
+- unref_list_count++;
+-
+- state->bo_count = exec->bo_count + unref_list_count;
+- kernel_state->bo = kcalloc(state->bo_count, sizeof(*kernel_state->bo),
+- GFP_ATOMIC);
++ /* Get the bos from both binner and renderer into hang state. */
++ state->bo_count = 0;
++ for (i = 0; i < 2; i++) {
++ if (!exec[i])
++ continue;
++
++ unref_list_count = 0;
++ list_for_each_entry(bo, &exec[i]->unref_list, unref_head)
++ unref_list_count++;
++ state->bo_count += exec[i]->bo_count + unref_list_count;
++ }
++
++ kernel_state->bo = kcalloc(state->bo_count,
++ sizeof(*kernel_state->bo), GFP_ATOMIC);
++
+ if (!kernel_state->bo) {
+ spin_unlock_irqrestore(&vc4->job_lock, irqflags);
+ return;
+ }
+
+- for (i = 0; i < exec->bo_count; i++) {
+- drm_gem_object_reference(&exec->bo[i]->base);
+- kernel_state->bo[i] = &exec->bo[i]->base;
+- }
++ prev_idx = 0;
++ for (i = 0; i < 2; i++) {
++ if (!exec[i])
++ continue;
++
++ for (j = 0; j < exec[i]->bo_count; j++) {
++ drm_gem_object_reference(&exec[i]->bo[j]->base);
++ kernel_state->bo[j + prev_idx] = &exec[i]->bo[j]->base;
++ }
+
+- list_for_each_entry(bo, &exec->unref_list, unref_head) {
+- drm_gem_object_reference(&bo->base.base);
+- kernel_state->bo[i] = &bo->base.base;
+- i++;
++ list_for_each_entry(bo, &exec[i]->unref_list, unref_head) {
++ drm_gem_object_reference(&bo->base.base);
++ kernel_state->bo[j + prev_idx] = &bo->base.base;
++ j++;
++ }
++ prev_idx = j + 1;
+ }
+
+- state->start_bin = exec->ct0ca;
+- state->start_render = exec->ct1ca;
++ if (exec[0])
++ state->start_bin = exec[0]->ct0ca;
++ if (exec[1])
++ state->start_render = exec[1]->ct1ca;
+
+ spin_unlock_irqrestore(&vc4->job_lock, irqflags);
+
+@@ -272,13 +290,15 @@ vc4_hangcheck_elapsed(unsigned long data
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+ uint32_t ct0ca, ct1ca;
+ unsigned long irqflags;
+- struct vc4_exec_info *exec;
++ struct vc4_exec_info *bin_exec, *render_exec;
+
+ spin_lock_irqsave(&vc4->job_lock, irqflags);
+- exec = vc4_first_job(vc4);
++
++ bin_exec = vc4_first_bin_job(vc4);
++ render_exec = vc4_first_render_job(vc4);
+
+ /* If idle, we can stop watching for hangs. */
+- if (!exec) {
++ if (!bin_exec && !render_exec) {
+ spin_unlock_irqrestore(&vc4->job_lock, irqflags);
+ return;
+ }
+@@ -289,9 +309,12 @@ vc4_hangcheck_elapsed(unsigned long data
+ /* If we've made any progress in execution, rearm the timer
+ * and wait.
+ */
+- if (ct0ca != exec->last_ct0ca || ct1ca != exec->last_ct1ca) {
+- exec->last_ct0ca = ct0ca;
+- exec->last_ct1ca = ct1ca;
++ if ((bin_exec && ct0ca != bin_exec->last_ct0ca) ||
++ (render_exec && ct1ca != render_exec->last_ct1ca)) {
++ if (bin_exec)
++ bin_exec->last_ct0ca = ct0ca;
++ if (render_exec)
++ render_exec->last_ct1ca = ct1ca;
+ spin_unlock_irqrestore(&vc4->job_lock, irqflags);
+ vc4_queue_hangcheck(dev);
+ return;
+@@ -391,11 +414,13 @@ vc4_flush_caches(struct drm_device *dev)
+ * The job_lock should be held during this.
+ */
+ void
+-vc4_submit_next_job(struct drm_device *dev)
++vc4_submit_next_bin_job(struct drm_device *dev)
+ {
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+- struct vc4_exec_info *exec = vc4_first_job(vc4);
++ struct vc4_exec_info *exec;
+
++again:
++ exec = vc4_first_bin_job(vc4);
+ if (!exec)
+ return;
+
+@@ -405,11 +430,40 @@ vc4_submit_next_job(struct drm_device *d
+ V3D_WRITE(V3D_BPOA, 0);
+ V3D_WRITE(V3D_BPOS, 0);
+
+- if (exec->ct0ca != exec->ct0ea)
++ /* Either put the job in the binner if it uses the binner, or
++ * immediately move it to the to-be-rendered queue.
++ */
++ if (exec->ct0ca != exec->ct0ea) {
+ submit_cl(dev, 0, exec->ct0ca, exec->ct0ea);
++ } else {
++ vc4_move_job_to_render(dev, exec);
++ goto again;
++ }
++}
++
++void
++vc4_submit_next_render_job(struct drm_device *dev)
++{
++ struct vc4_dev *vc4 = to_vc4_dev(dev);
++ struct vc4_exec_info *exec = vc4_first_render_job(vc4);
++
++ if (!exec)
++ return;
++
+ submit_cl(dev, 1, exec->ct1ca, exec->ct1ea);
+ }
+
++void
++vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec)
++{
++ struct vc4_dev *vc4 = to_vc4_dev(dev);
++ bool was_empty = list_empty(&vc4->render_job_list);
++
++ list_move_tail(&exec->head, &vc4->render_job_list);
++ if (was_empty)
++ vc4_submit_next_render_job(dev);
++}
++
+ static void
+ vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t seqno)
+ {
+@@ -448,14 +502,14 @@ vc4_queue_submit(struct drm_device *dev,
+ exec->seqno = seqno;
+ vc4_update_bo_seqnos(exec, seqno);
+
+- list_add_tail(&exec->head, &vc4->job_list);
++ list_add_tail(&exec->head, &vc4->bin_job_list);
+
+ /* If no job was executing, kick ours off. Otherwise, it'll
+- * get started when the previous job's frame done interrupt
++ * get started when the previous job's flush done interrupt
+ * occurs.
+ */
+- if (vc4_first_job(vc4) == exec) {
+- vc4_submit_next_job(dev);
++ if (vc4_first_bin_job(vc4) == exec) {
++ vc4_submit_next_bin_job(dev);
+ vc4_queue_hangcheck(dev);
+ }
+
+@@ -849,7 +903,8 @@ vc4_gem_init(struct drm_device *dev)
+ {
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+
+- INIT_LIST_HEAD(&vc4->job_list);
++ INIT_LIST_HEAD(&vc4->bin_job_list);
++ INIT_LIST_HEAD(&vc4->render_job_list);
+ INIT_LIST_HEAD(&vc4->job_done_list);
+ INIT_LIST_HEAD(&vc4->seqno_cb_list);
+ spin_lock_init(&vc4->job_lock);
+--- a/drivers/gpu/drm/vc4/vc4_irq.c
++++ b/drivers/gpu/drm/vc4/vc4_irq.c
+@@ -30,6 +30,10 @@
+ * disables that specific interrupt, and 0s written are ignored
+ * (reading either one returns the set of enabled interrupts).
+ *
++ * When we take a binning flush done interrupt, we need to submit the
++ * next frame for binning and move the finished frame to the render
++ * thread.
++ *
+ * When we take a render frame interrupt, we need to wake the
+ * processes waiting for some frame to be done, and get the next frame
+ * submitted ASAP (so the hardware doesn't sit idle when there's work
+@@ -44,6 +48,7 @@
+ #include "vc4_regs.h"
+
+ #define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
++ V3D_INT_FLDONE | \
+ V3D_INT_FRDONE)
+
+ DECLARE_WAIT_QUEUE_HEAD(render_wait);
+@@ -77,7 +82,7 @@ vc4_overflow_mem_work(struct work_struct
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&vc4->job_lock, irqflags);
+- current_exec = vc4_first_job(vc4);
++ current_exec = vc4_first_bin_job(vc4);
+ if (current_exec) {
+ vc4->overflow_mem->seqno = vc4->finished_seqno + 1;
+ list_add_tail(&vc4->overflow_mem->unref_head,
+@@ -98,17 +103,43 @@ vc4_overflow_mem_work(struct work_struct
+ }
+
+ static void
+-vc4_irq_finish_job(struct drm_device *dev)
++vc4_irq_finish_bin_job(struct drm_device *dev)
++{
++ struct vc4_dev *vc4 = to_vc4_dev(dev);
++ struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
++
++ if (!exec)
++ return;
++
++ vc4_move_job_to_render(dev, exec);
++ vc4_submit_next_bin_job(dev);
++}
++
++static void
++vc4_cancel_bin_job(struct drm_device *dev)
++{
++ struct vc4_dev *vc4 = to_vc4_dev(dev);
++ struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
++
++ if (!exec)
++ return;
++
++ list_move_tail(&exec->head, &vc4->bin_job_list);
++ vc4_submit_next_bin_job(dev);
++}
++
++static void
++vc4_irq_finish_render_job(struct drm_device *dev)
+ {
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+- struct vc4_exec_info *exec = vc4_first_job(vc4);
++ struct vc4_exec_info *exec = vc4_first_render_job(vc4);
+
+ if (!exec)
+ return;
+
+ vc4->finished_seqno++;
+ list_move_tail(&exec->head, &vc4->job_done_list);
+- vc4_submit_next_job(dev);
++ vc4_submit_next_render_job(dev);
+
+ wake_up_all(&vc4->job_wait_queue);
+ schedule_work(&vc4->job_done_work);
+@@ -125,9 +156,10 @@ vc4_irq(int irq, void *arg)
+ barrier();
+ intctl = V3D_READ(V3D_INTCTL);
+
+- /* Acknowledge the interrupts we're handling here. The render
+- * frame done interrupt will be cleared, while OUTOMEM will
+- * stay high until the underlying cause is cleared.
++ /* Acknowledge the interrupts we're handling here. The binner
++ * last flush / render frame done interrupt will be cleared,
++ * while OUTOMEM will stay high until the underlying cause is
++ * cleared.
+ */
+ V3D_WRITE(V3D_INTCTL, intctl);
+
+@@ -138,9 +170,16 @@ vc4_irq(int irq, void *arg)
+ status = IRQ_HANDLED;
+ }
+
++ if (intctl & V3D_INT_FLDONE) {
++ spin_lock(&vc4->job_lock);
++ vc4_irq_finish_bin_job(dev);
++ spin_unlock(&vc4->job_lock);
++ status = IRQ_HANDLED;
++ }
++
+ if (intctl & V3D_INT_FRDONE) {
+ spin_lock(&vc4->job_lock);
+- vc4_irq_finish_job(dev);
++ vc4_irq_finish_render_job(dev);
+ spin_unlock(&vc4->job_lock);
+ status = IRQ_HANDLED;
+ }
+@@ -205,6 +244,7 @@ void vc4_irq_reset(struct drm_device *de
+ V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
+
+ spin_lock_irqsave(&vc4->job_lock, irqflags);
+- vc4_irq_finish_job(dev);
++ vc4_cancel_bin_job(dev);
++ vc4_irq_finish_render_job(dev);
+ spin_unlock_irqrestore(&vc4->job_lock, irqflags);
+ }
--- /dev/null
+From 10f0d3fb0d155b0a6837f56a5e6a663a33d003ba Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 29 Feb 2016 17:53:00 -0800
+Subject: [PATCH 295/304] drm/vc4: Let gpiolib know that we're OK with sleeping
+ for HPD.
+
+Fixes an error thrown every few seconds when we poll HPD when it's on
+a I2C to GPIO expander.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Tested-by: Daniel Stone <daniels@collabora.com>
+(cherry picked from commit 0e60eab57557bc06bb3a5ef8d5d6dcd9ddd47aff)
+---
+ drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
++++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
+@@ -168,7 +168,7 @@ vc4_hdmi_connector_detect(struct drm_con
+ return connector_status_connected;
+
+ if (vc4->hdmi->hpd_gpio) {
+- if (gpio_get_value(vc4->hdmi->hpd_gpio))
++ if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio))
+ return connector_status_connected;
+ else
+ return connector_status_disconnected;
--- /dev/null
+From 4be409839b81a2fd724efc4cda01395130e20910 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Mon, 29 Feb 2016 17:53:01 -0800
+Subject: [PATCH 296/304] drm/vc4: Respect GPIO_ACTIVE_LOW on HDMI HPD if set
+ in the devicetree.
+
+The original Raspberry Pi had the GPIO active high, but the later
+models are active low. The DT GPIO bindings allow specifying the
+active flag, except that it doesn't get propagated to the gpiodesc, so
+you have to handle it yourself.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Tested-by: Daniel Stone <daniels@collabora.com>
+(cherry picked from commit 0b06e0a7945130e6a187f7959529cba7725f573a)
+---
+ drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
++++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
+@@ -47,6 +47,7 @@ struct vc4_hdmi {
+ void __iomem *hdmicore_regs;
+ void __iomem *hd_regs;
+ int hpd_gpio;
++ bool hpd_active_low;
+
+ struct clk *pixel_clock;
+ struct clk *hsm_clock;
+@@ -168,7 +169,8 @@ vc4_hdmi_connector_detect(struct drm_con
+ return connector_status_connected;
+
+ if (vc4->hdmi->hpd_gpio) {
+- if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio))
++ if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
++ vc4->hdmi->hpd_active_low)
+ return connector_status_connected;
+ else
+ return connector_status_disconnected;
+@@ -519,11 +521,17 @@ static int vc4_hdmi_bind(struct device *
+ * we'll use the HDMI core's register.
+ */
+ if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
+- hdmi->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
++ enum of_gpio_flags hpd_gpio_flags;
++
++ hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
++ "hpd-gpios", 0,
++ &hpd_gpio_flags);
+ if (hdmi->hpd_gpio < 0) {
+ ret = hdmi->hpd_gpio;
+ goto err_unprepare_hsm;
+ }
++
++ hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
+ }
+
+ vc4->hdmi = hdmi;
--- /dev/null
+From 5ae2b2779bed5095268019d56394420e7c751c29 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Tue, 8 Mar 2016 15:09:41 +0300
+Subject: [PATCH 297/304] drm/vc4: Return -EFAULT on copy_from_user() failure
+
+The copy_from_user() function returns the number of bytes not copied but
+we want to return a negative error code.
+
+Fixes: 463873d57014 ('drm/vc4: Add an API for creating GPU shaders in GEM BOs.')
+Cc: stable@vger.kernel.org
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+(cherry picked from commit 585cb132a48190b554aecda2ebc3e2911fcbb665)
+---
+ drivers/gpu/drm/vc4/vc4_bo.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/vc4/vc4_bo.c
++++ b/drivers/gpu/drm/vc4/vc4_bo.c
+@@ -519,11 +519,12 @@ vc4_create_shader_bo_ioctl(struct drm_de
+ if (IS_ERR(bo))
+ return PTR_ERR(bo);
+
+- ret = copy_from_user(bo->base.vaddr,
++ if (copy_from_user(bo->base.vaddr,
+ (void __user *)(uintptr_t)args->data,
+- args->size);
+- if (ret != 0)
++ args->size)) {
++ ret = -EFAULT;
+ goto fail;
++ }
+ /* Clear the rest of the memory from allocating from the BO
+ * cache.
+ */
--- /dev/null
+From fc45e6dc816d76b839a6efad3ee5bbb4def966c8 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Fri, 4 Mar 2016 12:32:07 -0800
+Subject: [PATCH 298/304] drm/vc4: Recognize a more specific compatible string
+ for V3D.
+
+The Raspberry Pi Foundation's firmware updates are shipping device
+trees using the old string, so we'll keep recognizing that as this rev
+of V3D. Still, we should use a more specific name in the upstream DT
+to clarify which board is being supported, in case we do other revs of
+V3D in the future.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Acked-by: Stephen Warren <swarren@wwwdotorg.org>
+(cherry picked from commit 90d7116061f86c1f8ea460806a0414addea7b58b)
+---
+ drivers/gpu/drm/vc4/vc4_v3d.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/vc4/vc4_v3d.c
++++ b/drivers/gpu/drm/vc4/vc4_v3d.c
+@@ -256,6 +256,7 @@ static int vc4_v3d_dev_remove(struct pla
+ }
+
+ static const struct of_device_id vc4_v3d_dt_match[] = {
++ { .compatible = "brcm,bcm2835-v3d" },
+ { .compatible = "brcm,vc4-v3d" },
+ {}
+ };
--- /dev/null
+From 08a0e34ea6911206ad18cec68ab1089505b0090a Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 19 Apr 2016 17:21:06 -0700
+Subject: [PATCH 299/304] ARM: bcm2708: Move the CMA range down for kernel 4.4.
+
+The previous area no longer works, for reasons I haven't investigated.
+Just move it somewhere that works.
+
+Signed-off-by: Eric Anholt <eric@anholt.net>
+---
+ arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
++++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts
+@@ -91,7 +91,7 @@
+ fragment@4 {
+ target-path = "/chosen";
+ __overlay__ {
+- bootargs = "cma=256M@512M";
++ bootargs = "cma=256M@256M";
+ };
+ };
+ };
--- /dev/null
+From 2b3a67805c0b48fce377b60237ee29edf90996ee Mon Sep 17 00:00:00 2001
+From: Vladimir Zapolskiy <vz@mleia.com>
+Date: Sun, 6 Mar 2016 03:21:35 +0200
+Subject: [PATCH 300/304] clk: bcm2835: fix check of error code returned by
+ devm_ioremap_resource()
+
+The change fixes potential oops while accessing iomem on invalid
+address, if devm_ioremap_resource() fails due to some reason.
+
+The devm_ioremap_resource() function returns ERR_PTR() and never
+returns NULL, which makes useless a following check for NULL.
+
+Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
+Fixes: 5e63dcc74b30 ("clk: bcm2835: Add a driver for the auxiliary peripheral clock gates")
+Reviewed-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+---
+ drivers/clk/bcm/clk-bcm2835-aux.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/bcm/clk-bcm2835-aux.c
++++ b/drivers/clk/bcm/clk-bcm2835-aux.c
+@@ -38,8 +38,8 @@ static int bcm2835_aux_clk_probe(struct
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg = devm_ioremap_resource(dev, res);
+- if (!reg)
+- return -ENODEV;
++ if (IS_ERR(reg))
++ return PTR_ERR(reg);
+
+ onecell = devm_kmalloc(dev, sizeof(*onecell), GFP_KERNEL);
+ if (!onecell)
--- /dev/null
+From 48b162fd15cc5a39d244f7c339786df4aa4c2c4d Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Thu, 21 Apr 2016 13:49:32 +0100
+Subject: [PATCH 301/304] vchiq_arm: Add completion records under the mutex
+
+An issue was observed when flushing openmax components
+which generate a large number of messages returning
+buffers to host.
+
+We occasionally found a duplicate message from 16
+messages prior, resulting in a buffer returned twice.
+
+While only one thread adds completions, without the
+mutex you don't get the protection of the automatic
+memory barrier you get with synchronisation objects.
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c
++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c
+@@ -210,6 +210,8 @@ add_completion(VCHIQ_INSTANCE_T instance
+ VCHIQ_COMPLETION_DATA_T *completion;
+ DEBUG_INITIALISE(g_state.local)
+
++ mutex_lock(&instance->completion_mutex);
++
+ while (instance->completion_insert ==
+ (instance->completion_remove + MAX_COMPLETIONS)) {
+ /* Out of space - wait for the client */
+@@ -217,11 +219,17 @@ add_completion(VCHIQ_INSTANCE_T instance
+ vchiq_log_trace(vchiq_arm_log_level,
+ "add_completion - completion queue full");
+ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT);
++
++ mutex_unlock(&instance->completion_mutex);
+ if (down_interruptible(&instance->remove_event) != 0) {
+ vchiq_log_info(vchiq_arm_log_level,
+ "service_callback interrupted");
+ return VCHIQ_RETRY;
+- } else if (instance->closing) {
++ }
++
++ mutex_lock(&instance->completion_mutex);
++ if (instance->closing) {
++ mutex_unlock(&instance->completion_mutex);
+ vchiq_log_info(vchiq_arm_log_level,
+ "service_callback closing");
+ return VCHIQ_SUCCESS;
+@@ -254,8 +262,11 @@ add_completion(VCHIQ_INSTANCE_T instance
+ if (reason == VCHIQ_MESSAGE_AVAILABLE)
+ user_service->message_available_pos =
+ instance->completion_insert;
++
+ instance->completion_insert++;
+
++ mutex_unlock(&instance->completion_mutex);
++
+ up(&instance->insert_event);
+
+ return VCHIQ_SUCCESS;
--- /dev/null
+From cb1ee7f3f3df6a311f2c5c353ae1792c1f9c2881 Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Thu, 21 Apr 2016 16:07:15 +0100
+Subject: [PATCH 302/304] config: Add DRM_UDL module
+
+See: https://github.com/raspberrypi/linux/issues/1422
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ arch/arm/configs/bcm2709_defconfig | 5 +++--
+ arch/arm/configs/bcmrpi_defconfig | 5 +++--
+ 2 files changed, 6 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/configs/bcm2709_defconfig
++++ b/arch/arm/configs/bcm2709_defconfig
+@@ -815,6 +815,7 @@ CONFIG_VIDEO_TW9906=m
+ CONFIG_VIDEO_OV7640=m
+ CONFIG_VIDEO_MT9V011=m
+ CONFIG_DRM=m
++CONFIG_DRM_UDL=m
+ CONFIG_DRM_VC4=m
+ CONFIG_FB=y
+ CONFIG_FB_BCM2708=y
+@@ -854,10 +855,10 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
+-CONFIG_SND_BCM2708_SOC_BOOMBERRY_DAC=m
+-CONFIG_SND_BCM2708_SOC_BOOMBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_RPI_DAC=m
+ CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
++CONFIG_SND_BCM2708_SOC_BOOMBERRY_DAC=m
++CONFIG_SND_BCM2708_SOC_BOOMBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
+ CONFIG_SND_BCM2708_SOC_RASPIDAC3=m
+ CONFIG_SND_SOC_ADAU1701=m
+--- a/arch/arm/configs/bcmrpi_defconfig
++++ b/arch/arm/configs/bcmrpi_defconfig
+@@ -807,6 +807,7 @@ CONFIG_VIDEO_TW9906=m
+ CONFIG_VIDEO_OV7640=m
+ CONFIG_VIDEO_MT9V011=m
+ CONFIG_DRM=m
++CONFIG_DRM_UDL=m
+ CONFIG_DRM_VC4=m
+ CONFIG_FB=y
+ CONFIG_FB_BCM2708=y
+@@ -846,10 +847,10 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
+-CONFIG_SND_BCM2708_SOC_BOOMBERRY_DAC=m
+-CONFIG_SND_BCM2708_SOC_BOOMBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_RPI_DAC=m
+ CONFIG_SND_BCM2708_SOC_RPI_PROTO=m
++CONFIG_SND_BCM2708_SOC_BOOMBERRY_DAC=m
++CONFIG_SND_BCM2708_SOC_BOOMBERRY_DIGI=m
+ CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
+ CONFIG_SND_BCM2708_SOC_RASPIDAC3=m
+ CONFIG_SND_SOC_ADAU1701=m
--- /dev/null
+From ddb9af17e2f52474d45c0afc04abc2af4510110e Mon Sep 17 00:00:00 2001
+From: Phil Elwell <phil@raspberrypi.org>
+Date: Thu, 21 Apr 2016 15:44:14 +0100
+Subject: [PATCH 303/304] bcm2835-i2s: Reduce the TX DREQ threshold
+
+TX FIFO overrun is thought to be the cause of channel swapping, so
+reducing the DREQ threshold seems reasonable and appears to be
+effective.
+
+See: https://github.com/raspberrypi/linux/issues/1417
+
+Signed-off-by: Phil Elwell <phil@raspberrypi.org>
+---
+ sound/soc/bcm/bcm2835-i2s.c | 21 ++++++++++++++-------
+ 1 file changed, 14 insertions(+), 7 deletions(-)
+
+--- a/sound/soc/bcm/bcm2835-i2s.c
++++ b/sound/soc/bcm/bcm2835-i2s.c
+@@ -555,15 +555,22 @@ static int bcm2835_i2s_hw_params(struct
+
+ /* Setup the DMA parameters */
+ regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
+- BCM2835_I2S_RXTHR(1)
+- | BCM2835_I2S_TXTHR(1)
+- | BCM2835_I2S_DMAEN, 0xffffffff);
++ BCM2835_I2S_RXTHR(3)
++ | BCM2835_I2S_TXTHR(3)
++ | BCM2835_I2S_DMAEN,
++ BCM2835_I2S_RXTHR(1)
++ | BCM2835_I2S_TXTHR(1)
++ | BCM2835_I2S_DMAEN);
+
+ regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG,
+- BCM2835_I2S_TX_PANIC(0x10)
+- | BCM2835_I2S_RX_PANIC(0x30)
+- | BCM2835_I2S_TX(0x30)
+- | BCM2835_I2S_RX(0x20), 0xffffffff);
++ BCM2835_I2S_TX_PANIC(0x7f)
++ | BCM2835_I2S_RX_PANIC(0x7f)
++ | BCM2835_I2S_TX(0x7f)
++ | BCM2835_I2S_RX(0x7f),
++ BCM2835_I2S_TX_PANIC(0x10)
++ | BCM2835_I2S_RX_PANIC(0x30)
++ | BCM2835_I2S_TX(0x20)
++ | BCM2835_I2S_RX(0x20));
+
+ /* Clear FIFOs */
+ bcm2835_i2s_clear_fifos(dev, true, true);
--- /dev/null
+From 0a2bdc152d2a9f8e0709fa4bd42fa75190b01e57 Mon Sep 17 00:00:00 2001
+From: Dave Stevenson <6by9@users.noreply.github.com>
+Date: Sat, 16 Apr 2016 23:09:54 +0100
+Subject: [PATCH 304/304] V4L2: Request maximum resolution from GPU
+
+Get resolution information about the sensors from the GPU
+and advertise it correctly.
+
+Signed-off-by: Dave Stevenson <6by9@users.noreply.github.com>
+---
+ drivers/media/platform/bcm2835/bcm2835-camera.c | 59 +++++++++++++++++--------
+ drivers/media/platform/bcm2835/bcm2835-camera.h | 3 +-
+ 2 files changed, 43 insertions(+), 19 deletions(-)
+
+--- a/drivers/media/platform/bcm2835/bcm2835-camera.c
++++ b/drivers/media/platform/bcm2835/bcm2835-camera.c
+@@ -38,8 +38,6 @@
+ #define BM2835_MMAL_MODULE_NAME "bcm2835-v4l2"
+ #define MIN_WIDTH 16
+ #define MIN_HEIGHT 16
+-#define MAX_WIDTH 2592
+-#define MAX_HEIGHT 1944
+ #define MIN_BUFFER_SIZE (80*1024)
+
+ #define MAX_VIDEO_MODE_WIDTH 1280
+@@ -729,11 +727,11 @@ static int vidioc_try_fmt_vid_overlay(st
+ f->fmt.win.clipcount = 0;
+ f->fmt.win.bitmap = NULL;
+
+- v4l_bound_align_image(&f->fmt.win.w.width, MIN_WIDTH, MAX_WIDTH, 1,
+- &f->fmt.win.w.height, MIN_HEIGHT, MAX_HEIGHT,
++ v4l_bound_align_image(&f->fmt.win.w.width, MIN_WIDTH, dev->max_width, 1,
++ &f->fmt.win.w.height, MIN_HEIGHT, dev->max_height,
+ 1, 0);
+- v4l_bound_align_image(&f->fmt.win.w.left, MIN_WIDTH, MAX_WIDTH, 1,
+- &f->fmt.win.w.top, MIN_HEIGHT, MAX_HEIGHT,
++ v4l_bound_align_image(&f->fmt.win.w.left, MIN_WIDTH, dev->max_width, 1,
++ &f->fmt.win.w.top, MIN_HEIGHT, dev->max_height,
+ 1, 0);
+
+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev,
+@@ -961,8 +959,9 @@ static int vidioc_try_fmt_vid_cap(struct
+ "Clipping/aligning %dx%d format %08X\n",
+ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat);
+
+- v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 1,
+- &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 1, 0);
++ v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, dev->max_width, 1,
++ &f->fmt.pix.height, MIN_HEIGHT, dev->max_height,
++ 1, 0);
+ f->fmt.pix.bytesperline = f->fmt.pix.width * mfmt->ybbp;
+
+ /* Image buffer has to be padded to allow for alignment, even though
+@@ -1301,9 +1300,10 @@ static int vidioc_s_fmt_vid_cap(struct f
+ int vidioc_enum_framesizes(struct file *file, void *fh,
+ struct v4l2_frmsizeenum *fsize)
+ {
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
+ static const struct v4l2_frmsize_stepwise sizes = {
+- MIN_WIDTH, MAX_WIDTH, 2,
+- MIN_HEIGHT, MAX_HEIGHT, 2
++ MIN_WIDTH, 0, 2,
++ MIN_HEIGHT, 0, 2
+ };
+ int i;
+
+@@ -1316,6 +1316,8 @@ int vidioc_enum_framesizes(struct file *
+ return -EINVAL;
+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
+ fsize->stepwise = sizes;
++ fsize->stepwise.max_width = dev->max_width;
++ fsize->stepwise.max_height = dev->max_height;
+ return 0;
+ }
+
+@@ -1323,6 +1325,7 @@ int vidioc_enum_framesizes(struct file *
+ static int vidioc_enum_frameintervals(struct file *file, void *priv,
+ struct v4l2_frmivalenum *fival)
+ {
++ struct bm2835_mmal_dev *dev = video_drvdata(file);
+ int i;
+
+ if (fival->index)
+@@ -1335,8 +1338,8 @@ static int vidioc_enum_frameintervals(st
+ return -EINVAL;
+
+ /* regarding width & height - we support any within range */
+- if (fival->width < MIN_WIDTH || fival->width > MAX_WIDTH ||
+- fival->height < MIN_HEIGHT || fival->height > MAX_HEIGHT)
++ if (fival->width < MIN_WIDTH || fival->width > dev->max_width ||
++ fival->height < MIN_HEIGHT || fival->height > dev->max_height)
+ return -EINVAL;
+
+ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
+@@ -1499,12 +1502,17 @@ static struct video_device vdev_template
+ .release = video_device_release_empty,
+ };
+
+-static int get_num_cameras(struct vchiq_mmal_instance *instance)
++/* Returns the number of cameras, and also the max resolution supported
++ * by those cameras.
++ */
++static int get_num_cameras(struct vchiq_mmal_instance *instance,
++ unsigned int resolutions[][2], int num_resolutions)
+ {
+ int ret;
+ struct vchiq_mmal_component *cam_info_component;
+ struct mmal_parameter_camera_info_t cam_info = {0};
+ int param_size = sizeof(cam_info);
++ int i;
+
+ /* create a camera_info component */
+ ret = vchiq_mmal_component_init(instance, "camera_info",
+@@ -1520,6 +1528,14 @@ static int get_num_cameras(struct vchiq_
+ ¶m_size)) {
+ pr_info("Failed to get camera info\n");
+ }
++ for (i = 0;
++ i < (cam_info.num_cameras > num_resolutions ?
++ cam_info.num_cameras :
++ num_resolutions);
++ i++) {
++ resolutions[i][0] = cam_info.cameras[i].max_width;
++ resolutions[i][1] = cam_info.cameras[i].max_height;
++ }
+
+ vchiq_mmal_component_finalise(instance,
+ cam_info_component);
+@@ -1528,12 +1544,13 @@ static int get_num_cameras(struct vchiq_
+ }
+
+ static int set_camera_parameters(struct vchiq_mmal_instance *instance,
+- struct vchiq_mmal_component *camera)
++ struct vchiq_mmal_component *camera,
++ struct bm2835_mmal_dev *dev)
+ {
+ int ret;
+ struct mmal_parameter_camera_config cam_config = {
+- .max_stills_w = MAX_WIDTH,
+- .max_stills_h = MAX_HEIGHT,
++ .max_stills_w = dev->max_width,
++ .max_stills_h = dev->max_height,
+ .stills_yuv422 = 1,
+ .one_shot_stills = 1,
+ .max_preview_video_w = (max_video_width > 1920) ?
+@@ -1576,7 +1593,8 @@ static int __init mmal_init(struct bm283
+ }
+
+ ret = set_camera_parameters(dev->instance,
+- dev->component[MMAL_COMPONENT_CAMERA]);
++ dev->component[MMAL_COMPONENT_CAMERA],
++ dev);
+ if (ret < 0)
+ goto unreg_camera;
+
+@@ -1838,12 +1856,15 @@ static int __init bm2835_mmal_init(void)
+ int camera;
+ unsigned int num_cameras;
+ struct vchiq_mmal_instance *instance;
++ unsigned int resolutions[MAX_BCM2835_CAMERAS][2];
+
+ ret = vchiq_mmal_init(&instance);
+ if (ret < 0)
+ return ret;
+
+- num_cameras = get_num_cameras(instance);
++ num_cameras = get_num_cameras(instance,
++ resolutions,
++ MAX_BCM2835_CAMERAS);
+ if (num_cameras > MAX_BCM2835_CAMERAS)
+ num_cameras = MAX_BCM2835_CAMERAS;
+
+@@ -1853,6 +1874,8 @@ static int __init bm2835_mmal_init(void)
+ return -ENOMEM;
+
+ dev->camera_num = camera;
++ dev->max_width = resolutions[camera][0];
++ dev->max_height = resolutions[camera][1];
+
+ /* setup device defaults */
+ dev->overlay.w.left = 150;
+--- a/drivers/media/platform/bcm2835/bcm2835-camera.h
++++ b/drivers/media/platform/bcm2835/bcm2835-camera.h
+@@ -107,7 +107,8 @@ struct bm2835_mmal_dev {
+ } capture;
+
+ unsigned int camera_num;
+-
++ unsigned int max_width;
++ unsigned int max_height;
+ };
+
+ int bm2835_mmal_init_controls(
projects / thirdparty / openwrt.git / commitdiff
