]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
i2c: riic: Add support for RZ/T2H SoC
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Wed, 25 Jun 2025 10:45:26 +0000 (11:45 +0100)
committerAndi Shyti <andi.shyti@kernel.org>
Wed, 23 Jul 2025 22:37:59 +0000 (00:37 +0200)
Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a
different interrupt layout for the RIIC controller. Unlike other SoCs
with individual error interrupts, RZ/T2H uses a combined error interrupt
(EEI).

Introduce a new IRQ descriptor table for RZ/T2H, along with a custom
ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared
interrupt.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # on RZ/A1
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250625104526.101004-6-prabhakar.mahadev-lad.rj@bp.renesas.com
drivers/i2c/busses/i2c-riic.c

index d0b975e45595a4ef55353f20bebe1d81c99a8336..9c164a4b9bb91c794a85d1136b82542957c163a5 100644 (file)
@@ -79,6 +79,7 @@
 #define ICIER_SPIE     BIT(3)
 
 #define ICSR2_NACKF    BIT(4)
+#define ICSR2_STOP     BIT(3)
 
 #define ICBR_RESERVED  GENMASK(7, 5) /* Should be 1 on writes */
 
@@ -326,6 +327,19 @@ static irqreturn_t riic_stop_isr(int irq, void *data)
        return IRQ_HANDLED;
 }
 
+static irqreturn_t riic_eei_isr(int irq, void *data)
+{
+       u8 icsr2 = riic_readb(data, RIIC_ICSR2);
+
+       if (icsr2 & ICSR2_NACKF)
+               return riic_tend_isr(irq, data);
+
+       if (icsr2 & ICSR2_STOP)
+               return riic_stop_isr(irq, data);
+
+       return IRQ_NONE;
+}
+
 static u32 riic_func(struct i2c_adapter *adap)
 {
        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -497,6 +511,13 @@ static const struct riic_irq_desc riic_irqs[] = {
        { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
 };
 
+static const struct riic_irq_desc riic_rzt2h_irqs[] = {
+       { .res_num = 0, .isr = riic_eei_isr,  .name = "riic-eei" },
+       { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rxi" },
+       { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-txi" },
+       { .res_num = 3, .isr = riic_tend_isr, .name = "riic-tei" },
+};
+
 static int riic_i2c_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
@@ -643,6 +664,12 @@ static const struct riic_of_data riic_rz_v2h_info = {
        .fast_mode_plus = true,
 };
 
+static const struct riic_of_data riic_rz_t2h_info = {
+       .regs = riic_rz_v2h_regs,
+       .irqs = riic_rzt2h_irqs,
+       .num_irqs = ARRAY_SIZE(riic_rzt2h_irqs),
+};
+
 static int riic_i2c_suspend(struct device *dev)
 {
        struct riic_dev *riic = dev_get_drvdata(dev);
@@ -695,6 +722,7 @@ static const struct dev_pm_ops riic_i2c_pm_ops = {
 static const struct of_device_id riic_i2c_dt_ids[] = {
        { .compatible = "renesas,riic-r7s72100", .data =  &riic_rz_a1h_info, },
        { .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info },
+       { .compatible = "renesas,riic-r9a09g077", .data = &riic_rz_t2h_info },
        { .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
        { /* Sentinel */ }
 };