RISC-V: Fix vec_duplicate[bimode] expander [PR119572].

Since r15-9062-g70391e3958db79 we perform vector bitmask initialization
via the vec_duplicate expander directly.  This triggered a latent bug in
ours where we missed to mask out the single bit which resulted in an
execution FAIL of pr119114.c

The attached patch adds the 1-masking of the broadcast operand.

	PR target/119572

gcc/ChangeLog:

	* config/riscv/autovec.md: Mask broadcast value.

(cherry picked from commit 716d39f0a248c1003033e6a312c736180790ef70)

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4b77e154ae70a2e3561b092e62181581278f1955..12107e2d15245573edd4a3a4ddbf76c6e720b9f0 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -321,7 +321,15 @@
   {
     poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode);
     machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require ();
-    rtx dup = expand_vector_broadcast (mode, operands[1]);
+
+    /* The 1-bit mask is in a QImode register, make sure we only use the last
+       bit.  See also PR119114 and the respective vec_init expander.  */
+    rtx tmp = gen_reg_rtx (Xmode);
+    emit_insn
+      (gen_rtx_SET (tmp, gen_rtx_AND (Xmode, gen_lowpart (Xmode, operands[1]),
+                                     CONST1_RTX (Xmode))));
+
+    rtx dup = expand_vector_broadcast (mode, gen_lowpart (QImode, tmp));
     riscv_vector::expand_vec_cmp (operands[0], NE, dup, CONST0_RTX (mode));
     DONE;
   }