]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
ARM: dts: renesas: r9a06g032: Add second clock input to RTC
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Wed, 4 Jun 2025 08:40:11 +0000 (10:40 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 19 Jun 2025 17:34:33 +0000 (19:34 +0200)
The external RTC clock is populated on the RZ/N1D module, so describe it
and add a reference to the RTC node.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250604084211.28090-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
arch/arm/boot/dts/renesas/r9a06g032.dtsi

index d734a432b3ec877e510acd625ff7b724fad49ec8..3258b2e274346d5c5d419ba3b3e8c4350c9af0c6 100644 (file)
        renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
 };
 
+&ext_rtc_clk {
+       clock-frequency = <32768>;
+};
+
 &gmac2 {
        status = "okay";
        phy-mode = "gmii";
index 80ad1fdc77a068ef343aeee8d7abeab565ef8e30..13a60656b0447084812fb2821b25f101e12ad8be 100644 (file)
@@ -73,8 +73,8 @@
                                     <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
                                     <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
                        interrupt-names = "alarm", "timer", "pps";
-                       clocks = <&sysctrl R9A06G032_HCLK_RTC>;
-                       clock-names = "hclk";
+                       clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>;
+                       clock-names = "hclk", "xtal";
                        power-domains = <&sysctrl>;
                        status = "disabled";
                };