arm64: dts: qcom: glymur: fix PCIe SMMU interrupts

The PCIe SMMUv3 wired interrupts are routed to GIC extended SPI INTIDs
4100, 4098 and 4096. Describe them as ESPIs with the ESPI-relative
interrupt numbers instead of regular SPIs 964, 962 and 960.

Assisted-by: Codex:GPT-5.5
Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260611-glymur-pcie-smmu-espi-v1-1-5effbaa3e1af@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 20b49af7298e9549d126aa50a0dc7a90943a3249..c7edfa8156f3afe3d31dc8e3f2c41669ead8f28b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -6874,9 +6874,9 @@
                pcie_smmu: iommu@15480000 {
                        compatible = "arm,smmu-v3";
                        reg = <0x0 0x15480000 0x0 0x20000>;
-                       interrupts = <GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 962 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_ESPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_ESPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_ESPI 0 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "eventq", "cmdq-sync", "gerror";
                        dma-coherent;
                        #iommu-cells = <1>;