RISC-V: Add test for vec_duplicate + vnmsac.vv signed combine with GR2VR cost 0,...

Add asm dump check and run test for vec_duplicate + vnmsac.vvm
combine to vnmsac.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vnmsac.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Add test
	helper macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index e99744c037bb7e4c1c980952a155ea97fd5ea80f..ad2dacd1f25ab5c6c85c181a0eb7d54264322f66 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 1f1f3d28d1358e0065dd17bf347f6b05cc3d0897..ebcdb0aeb0f989da7b431d2704da4db0e143eb94 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index f6bbfaea4386a49fff0a32dfe21f872eff726d20..f15d7b552072a6a76e237548cedd1cae1261b8bf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -27,3 +27,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
      "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4"
    } } } } */
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index d9fd498bc3daf52a0030e3509093ed1da92362a6..c9973485e0acbc4464b913160526a204759e72ab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vssub.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 5ddcc2d0767a3fed14282209d713605858859c06..db272ef0f49ee52028bfff406205d33fc9abc271 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 1b25d79ae55e1c2d1818ca27c996577d3d711529..b3f99ba7c8b356c40760c9af48d7c267fff18560 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 71507859bc88e77ae1507b71cf41f4012d6e0158..4fdf8f986fd09c77adf3234b45637a9309f8954a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 077fab91d8c49c1ced656bee9bc3f3a6957b952a..02cf934f943f688ae471714a2c5d7f6d688aacbc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 056f2c02c6b33014be68519d68c94dcc48dc4431..94f83ffe588f70201f04aa8b29a89016d20832a8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index f36939431d7795c542459de06d490ee07fcde468..77468092cfe91c5ff6c1d616fe27bb1d9e70bc3e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index bc00c6bc72714208a0b13a909e5e4f76cec4d693..ed31e7965ccbb4ca857c9c1a82a5bfdcb8a8cee0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index 15716f682270c5761f52f3039b31cea6f1469333..b9d1ddc039be17339a9f21c0a3004a0cec3e47ec 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -24,3 +24,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vssub.vx} } } */
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsac.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
index be54a3ad33dde2f616787a2e6b4dae5a017facd5..2325c7b863211f12e05ebf6ce28c645388e20401 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
@@ -28,8 +28,10 @@ test_vx_ternary_##NAME##_##T##_case_0 (T * restrict vd, T * restrict vs2, \
 
 #define TEST_TERNARY_VX_SIGNED_0(T)                                \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc)                        \
+  DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac)                       \
 
 #define TEST_TERNARY_VX_UNSIGNED_0(T)                              \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc)                        \
+  DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac)                       \
 
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
index 8fed997eeb871f4271ddc8d0210e0b02bfdde6a9..9ac1a7ddc3a836e2eab1949b73ea3472cfe428cc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
@@ -374,4 +374,372 @@ uint64_t TEST_TERNARY_DATA(uint64_t, macc)[][4][N] =
   },
 };
 
+int8_t TEST_TERNARY_DATA(int8_t, nmsac)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 127 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       127,  127,  127,  127,
+         2,    2,    2,    2,
+         0,    0,    0,    0,
+      -128, -128, -128, -128,
+    },
+    {
+       127,  127,  127,  127,
+      -125, -125, -125, -125,
+        -8,   -8,   -8,   -8,
+       126,  126,  126,  126,
+    },
+  },
+};
+
+int16_t TEST_TERNARY_DATA(int16_t, nmsac)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 32767 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       32767,  32767,  32767,  32767,
+           2,      2,      2,      2,
+           0,      0,      0,      0,
+      -32768, -32768, -32768, -32768,
+    },
+    {
+       32767,  32767,  32767,  32767,
+      -32765, -32765, -32765, -32765,
+          -8,     -8,     -8,     -8,
+       32766,  32766,  32766,  32766,
+    },
+  },
+};
+
+int32_t TEST_TERNARY_DATA(int32_t, nmsac)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 2147483647 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       2147483647,  2147483647,  2147483647,  2147483647,
+                2,           2,           2,           2,
+                0,           0,           0,           0,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+      -2147483645, -2147483645, -2147483645, -2147483645,
+               -8,          -8,          -8,          -8,
+       2147483646,  2147483646,  2147483646,  2147483646,
+    },
+  },
+};
+
+int64_t TEST_TERNARY_DATA(int64_t, nmsac)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+    },
+  },
+  {
+    { 9223372036854775807ull }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    { /* vd */
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+                            2,                       2,                       2,                       2,
+                            0,                       0,                       0,                       0,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+    },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+      -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull, -9223372036854775805ull,
+                           -8,                      -8,                      -8,                      -8,
+       9223372036854775806ull,  9223372036854775806ull,  9223372036854775806ull,  9223372036854775806ull,
+    },
+  },
+};
+
+uint8_t TEST_TERNARY_DATA(uint8_t, nmsac)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 128 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    { /* vd */
+       127,  127,  127,  127,
+       255,  255,  255,  255,
+       254,  254,  254,  254,
+       252,  252,  252,  252,
+    },
+    {
+       127,  127,  127,  127,
+       127,  127,  127,  127,
+       254,  254,  254,  254,
+       252,  252,  252,  252,
+    },
+  },
+};
+
+uint16_t TEST_TERNARY_DATA(uint16_t, nmsac)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 32768 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    { /* vd */
+       32767,  32767,  32767,  32767,
+       65535,  65535,  65535,  65535,
+       65534,  65534,  65534,  65534,
+       65532,  65532,  65532,  65532,
+    },
+    {
+       32767,  32767,  32767,  32767,
+       32767,  32767,  32767,  32767,
+       65534,  65534,  65534,  65534,
+       65532,  65532,  65532,  65532,
+    },
+  },
+};
+
+uint32_t TEST_TERNARY_DATA(uint32_t, nmsac)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 2147483648 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    { /* vd */
+       2147483647,  2147483647,  2147483647,  2147483647,
+       4294967295,  4294967295,  4294967295,  4294967295,
+       4294967294,  4294967294,  4294967294,  4294967294,
+       4294967292,  4294967292,  4294967292,  4294967292,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       2147483647,  2147483647,  2147483647,  2147483647,
+       4294967294,  4294967294,  4294967294,  4294967294,
+       4294967292,  4294967292,  4294967292,  4294967292,
+    },
+  },
+};
+
+uint64_t TEST_TERNARY_DATA(uint64_t, nmsac)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+    },
+    { /* vd */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       8,  8,  8,  8,
+       7,  7,  7,  7,
+    },
+    {
+       1,  1,  1,  1,
+       1,  1,  1,  1,
+       7,  7,  7,  7,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    { 9223372036854775808ull }, /* rs1 */
+    { /* vs2 */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+       8,  8,  8,  8,
+       2,  2,  2,  2,
+    },
+    { /* vd */
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+       18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,
+       18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,
+    },
+    {
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+        9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,   9223372036854775807ull,
+       18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,
+       18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,  18446744073709551612ull,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c
new file mode 100644 (file)
index 0000000..6deee02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int16_t
+#define NAME       nmsac
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c
new file mode 100644 (file)
index 0000000..65d376b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int32_t
+#define NAME       nmsac
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c
new file mode 100644 (file)
index 0000000..832023a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int64_t
+#define NAME       nmsac
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c
new file mode 100644 (file)
index 0000000..ae48e2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsac-run-1-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int8_t
+#define NAME       nmsac
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"