.pcs_config = dwmac_integrated_pcs_config,
};
-/**
- * stmmac_integrated_pcs_irq - TBI, RTBI, or SGMII PHY ISR
- * @ioaddr: IO registers pointer
- * @reg: Base address of the AN Control Register.
- * @intr_status: GMAC core interrupt status
- * @x: pointer to log these events as stats
- * Description: it is the ISR for PCS events: Auto-Negotiation Completed and
- * Link status.
- */
-void stmmac_integrated_pcs_irq(void __iomem *ioaddr, u32 reg,
- unsigned int intr_status,
+void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
struct stmmac_extra_stats *x)
{
- u32 val = readl(ioaddr + GMAC_AN_STATUS(reg));
+ struct stmmac_pcs *spcs = priv->integrated_pcs;
+ u32 val = readl(spcs->base + GMAC_AN_STATUS(0));
- if (intr_status & PCS_ANE_IRQ) {
+ if (status & PCS_ANE_IRQ) {
x->irq_pcs_ane_n++;
if (val & GMAC_AN_STATUS_ANC)
- pr_info("stmmac_pcs: ANE process completed\n");
+ dev_info(priv->device,
+ "PCS ANE process completed\n");
}
- if (intr_status & PCS_LINK_IRQ) {
+ if (status & PCS_LINK_IRQ) {
x->irq_pcs_link_n++;
- if (val & GMAC_AN_STATUS_LS)
- pr_info("stmmac_pcs: Link Up\n");
- else
- pr_info("stmmac_pcs: Link Down\n");
+ dev_info(priv->device, "PCS Link %s\n",
+ val & GMAC_AN_STATUS_LS ? "Up" : "Down");
}
}
return container_of(pcs, struct stmmac_pcs, pcs);
}
-void stmmac_integrated_pcs_irq(void __iomem *ioaddr, u32 reg,
- unsigned int intr_status,
+void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
struct stmmac_extra_stats *x);
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
u32 int_mask);