drm/amd/pm: fix smu v14 soft clock frequency setting issue

v1:
resolve the issue where some freq frequencies cannot be set correctly
due to insufficient floating-point precision.

v2:
patch this convert on 'max' value only.

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index 613d4d36f32fdf1400e78c563d1429bfebe0922d..b453e6efc7c9d3664b7dd6fc0a78496640aea520 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -56,6 +56,7 @@ extern const int decoded_link_width[8];
 
 #define DECODE_GEN_SPEED(gen_speed_idx)                (decoded_link_speed[gen_speed_idx])
 #define DECODE_LANE_WIDTH(lane_width_idx)      (decoded_link_width[lane_width_idx])
+#define SMU_V14_SOFT_FREQ_ROUND(x)     ((x) + 1)
 
 struct smu_14_0_max_sustainable_clocks {
        uint32_t display_clock;

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index f85ba23f9d99add2f954b8a99b7f70179830f330..17caf98bd6ddc2c380c9d44b7ef3da49b51a4356 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -1177,6 +1177,7 @@ int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu,
                return clk_id;
 
        if (max > 0) {
+               max = SMU_V14_SOFT_FREQ_ROUND(max);
                if (automatic)
                        param = (uint32_t)((clk_id << 16) | 0xffff);
                else