PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions.

These are Power 9 instructions.

Add test cases for the new instructions to test_isa_3_0.c

Bugzilla 385183.

diff --git a/NEWS b/NEWS
index 1ab22bbd4292086d78f22af9defe51f1270d3ae3..efa1f4a2b310e6df0c2992fe5597d862f5286ed8 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -62,6 +62,7 @@ n-i-bz  Fix missing workq_ops operations (macOS)
 385207  PPC64, generate_store_FPRF() generates too many Iops
 385208  PPC64, xxperm instruction exhausts temporary memory
 385210  PPC64, vpermr instruction could exhaust temporary memory
+385183  PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions
 
 Release 3.13.0 (15 June 2017)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 97664c2f76fb66a2523e7b640d19ad8e42c5fd85..6b2157d8614011e8c1f2c156fcdf8df53cbccf78 100644 (file)
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -3629,18 +3629,22 @@ static IRExpr * fp_exp_part( IRType size, IRTemp src )
 /* 16-bit floating point number is stored in the lower 16-bits of 32-bit value */
 #define I16_EXP_MASK       0x7C00
 #define I16_FRACTION_MASK  0x03FF
+#define I16_MSB_FRACTION_MASK  0x0200
 #define I32_EXP_MASK       0x7F800000
 #define I32_FRACTION_MASK  0x007FFFFF
+#define I32_MSB_FRACTION_MASK  0x00400000
 #define I64_EXP_MASK       0x7FF0000000000000ULL
 #define I64_FRACTION_MASK  0x000FFFFFFFFFFFFFULL
+#define I64_MSB_FRACTION_MASK  0x0008000000000000ULL
 #define V128_EXP_MASK      0x7FFF000000000000ULL
 #define V128_FRACTION_MASK 0x0000FFFFFFFFFFFFULL  /* upper 64-bit fractional mask */
+#define V128_MSB_FRACTION_MASK 0x0000800000000000ULL  /* upper 64-bit fractional mask */
 
 void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask,
-                             IRTemp *zero );
+                             IRTemp *msb_frac_mask, IRTemp *zero );
 
 void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask,
-                             IRTemp *zero ) {
+                             IRTemp *msb_frac_mask, IRTemp *zero ) {
 
    vassert( ( size == Ity_I16 ) || ( size == Ity_I32 )
             || ( size == Ity_I64 ) || ( size == Ity_V128 ) );
@@ -3649,37 +3653,45 @@ void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask,
       /* The 16-bit floating point value is in the lower 16-bits of
          the 32-bit input value */
       *frac_mask = newTemp( Ity_I32 );
+      *msb_frac_mask = newTemp( Ity_I32 );
       *exp_mask  = newTemp( Ity_I32 );
       *zero  = newTemp( Ity_I32 );
       assign( *exp_mask, mkU32( I16_EXP_MASK ) );
       assign( *frac_mask, mkU32( I16_FRACTION_MASK ) );
+      assign( *msb_frac_mask, mkU32( I16_MSB_FRACTION_MASK ) );
       assign( *zero, mkU32( 0 ) );
 
    } else if( size == Ity_I32 ) {
       *frac_mask = newTemp( Ity_I32 );
+      *msb_frac_mask = newTemp( Ity_I32 );
       *exp_mask  = newTemp( Ity_I32 );
       *zero  = newTemp( Ity_I32 );
       assign( *exp_mask, mkU32( I32_EXP_MASK ) );
       assign( *frac_mask, mkU32( I32_FRACTION_MASK ) );
+      assign( *msb_frac_mask, mkU32( I32_MSB_FRACTION_MASK ) );
       assign( *zero, mkU32( 0 ) );
 
    } else if( size == Ity_I64 ) {
       *frac_mask = newTemp( Ity_I64 );
+      *msb_frac_mask = newTemp( Ity_I64 );
       *exp_mask  = newTemp( Ity_I64 );
       *zero  = newTemp( Ity_I64 );
       assign( *exp_mask, mkU64( I64_EXP_MASK ) );
       assign( *frac_mask, mkU64( I64_FRACTION_MASK ) );
+      assign( *msb_frac_mask, mkU64( I64_MSB_FRACTION_MASK ) );
       assign( *zero, mkU64( 0 ) );
 
    } else {
       /* V128 is converted to upper and lower 64 bit values, */
       /* uses 64-bit operators and temps */
       *frac_mask = newTemp( Ity_I64 );
+      *msb_frac_mask = newTemp( Ity_I64 );
       *exp_mask  = newTemp( Ity_I64 );
       *zero  = newTemp( Ity_I64 );
       assign( *exp_mask, mkU64( V128_EXP_MASK ) );
       /* upper 64-bit fractional mask */
       assign( *frac_mask, mkU64( V128_FRACTION_MASK ) );
+      assign( *msb_frac_mask, mkU64( V128_MSB_FRACTION_MASK ) );
       assign( *zero, mkU64( 0 ) );
    }
 }
@@ -3801,9 +3813,10 @@ static IRExpr *fractional_part_compare( IRType size, IRTemp src,
 static IRExpr * is_Inf( IRType size, IRTemp src )
 {
    IRExpr *max_exp, *zero_frac;
-   IRTemp exp_mask, frac_mask, zero;
+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
 
-   setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+                           &zero );
 
    /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
    max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) );
@@ -3818,9 +3831,10 @@ static IRExpr * is_Inf( IRType size, IRTemp src )
 static IRExpr * is_Zero( IRType size, IRTemp src )
 {
    IRExpr *zero_exp, *zero_frac;
-   IRTemp exp_mask, frac_mask, zero;
+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
 
-   setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+                           &zero );
 
    /* check the exponent is all zeros, i.e. (exp AND exp_mask) = zero */
    zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) );
@@ -3837,9 +3851,10 @@ static IRExpr * is_Zero( IRType size, IRTemp src )
 static IRExpr * is_NaN( IRType size, IRTemp src )
 {
    IRExpr *max_exp, *not_zero_frac;
-   IRTemp exp_mask, frac_mask, zero;
+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
 
-   setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+                           &zero );
 
    /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
    max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) );
@@ -3852,13 +3867,37 @@ static IRExpr * is_NaN( IRType size, IRTemp src )
    return  mkAND1( max_exp, not_zero_frac );
 }
 
+static IRExpr * is_sNaN( IRType size, IRTemp src )
+{
+   IRExpr *max_exp, *not_zero_frac, *msb_zero;
+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
+
+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+                           &zero );
+
+   /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
+   max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) );
+
+   /* Most significant fractional bit is zero for sNaN */
+   msb_zero = fractional_part_compare ( size, src, msb_frac_mask,
+                                        mkexpr( zero ) );
+
+   /* check fractional part is not zero */
+   not_zero_frac = unop( Iop_Not1,
+                         fractional_part_compare( size, src, frac_mask,
+                                                  mkexpr( zero ) ) );
+
+   return  mkAND1( msb_zero, mkAND1( max_exp, not_zero_frac ) );
+}
+
 /* Denormalized number has a zero exponent and non zero fraction. */
 static IRExpr * is_Denorm( IRType size, IRTemp src )
 {
    IRExpr *zero_exp, *not_zero_frac;
-   IRTemp exp_mask, frac_mask, zero;
+   IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
 
-   setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
+   setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+                           &zero );
 
    /* check exponent is all zeros */
    zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) );
@@ -19711,6 +19750,216 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2,
    return True;
 }
 
+/*
+ * VSX vector miscellaneous instructions
+ */
+
+static Bool
+dis_vx_misc ( UInt theInstr, UInt opc2 )
+{
+   /* XX3-Form */
+   UChar XT = ifieldRegXT ( theInstr );
+   UChar XA = ifieldRegXA ( theInstr );
+   UChar XB = ifieldRegXB ( theInstr );
+   IRTemp vA = newTemp( Ity_V128 );
+   IRTemp vB = newTemp( Ity_V128 );
+   IRTemp src1 = newTemp(Ity_I64);
+   IRTemp src2 = newTemp(Ity_I64);
+   IRTemp result_mask = newTemp(Ity_I64);
+   IRTemp cmp_mask = newTemp(Ity_I64);
+   IRTemp nan_mask = newTemp(Ity_I64);
+   IRTemp snan_mask = newTemp(Ity_I64);
+   IRTemp word_result = newTemp(Ity_I64);
+   IRTemp check_result = newTemp(Ity_I64);
+   IRTemp xT = newTemp( Ity_V128 );
+   IRTemp nan_cmp_value = newTemp(Ity_I64);
+   UInt trap_enabled = 0;  /* 0 - trap enabled is False */
+
+   assign( vA, getVSReg( XA ) );
+   assign( vB, getVSReg( XB ) );
+   assign( xT, getVSReg( XT ) );
+
+   assign(src1, unop( Iop_V128HIto64, mkexpr( vA ) ) );
+   assign(src2, unop( Iop_V128HIto64, mkexpr( vB ) ) );
+
+   assign( nan_mask,
+           binop( Iop_Or64,
+                  unop( Iop_1Sto64, is_NaN( Ity_I64, src1 ) ),
+                  unop( Iop_1Sto64, is_NaN( Ity_I64, src2 ) ) ) );
+
+   if ( trap_enabled == 0 )
+      /* Traps on invalid operation are assumed not enabled, assign
+         result of comparison to xT.
+      */
+      assign( snan_mask, mkU64( 0 ) );
+
+   else
+      assign( snan_mask,
+              binop( Iop_Or64,
+                     unop( Iop_1Sto64, is_sNaN( Ity_I64, src1 ) ),
+                     unop( Iop_1Sto64, is_sNaN( Ity_I64, src2 ) ) ) );
+
+   assign (result_mask, binop( Iop_Or64,
+                               mkexpr( snan_mask ),
+                               mkexpr( nan_mask ) ) );
+
+   switch (opc2) {
+   case 0xC: //xscmpeqdp
+      {
+         DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB);
+         /* extract double-precision floating point source values from
+            double word 0 */
+
+         /* result of Iop_CmpF64 is 0x40 if operands are equal,
+            mask is all 1's if equal. */
+
+         assign( cmp_mask,
+                 unop( Iop_1Sto64,
+                       unop(Iop_32to1,
+                            binop(Iop_Shr32,
+                                  binop( Iop_CmpF64,
+                                         unop( Iop_ReinterpI64asF64,
+                                               mkexpr( src1 ) ),
+                                         unop( Iop_ReinterpI64asF64,
+                                               mkexpr( src2 ) ) ),
+                                  mkU8( 6 ) ) ) ) );
+
+         assign( word_result,
+                 binop( Iop_Or64,
+                        binop( Iop_And64, mkexpr( cmp_mask ),
+                               mkU64( 0xFFFFFFFFFFFFFFFF ) ),
+                        binop( Iop_And64,
+                               unop( Iop_Not64, mkexpr( cmp_mask ) ),
+                               mkU64( 0x0 ) ) ) );
+         assign( nan_cmp_value, mkU64( 0 ) );
+         break;
+      }
+
+   case 0x2C: //xscmpgtdp
+      {
+         DIP("xscmpgtdp v%d,v%d,v%d\n", XT, XA, XB);
+         /* Test for src1 > src2 */
+
+         /* Result of Iop_CmpF64 is 0x1 if op1 < op2, set mask to all 1's. */
+         assign( cmp_mask,
+                 unop( Iop_1Sto64,
+                       unop(Iop_32to1,
+                            binop(Iop_CmpF64,
+                                  unop( Iop_ReinterpI64asF64,
+                                        mkexpr( src2 ) ),
+                                  unop( Iop_ReinterpI64asF64,
+                                       mkexpr( src1 ) ) ) ) ) );
+         assign( word_result,
+                 binop( Iop_Or64,
+                        binop( Iop_And64, mkexpr( cmp_mask ),
+                               mkU64( 0xFFFFFFFFFFFFFFFF ) ),
+                        binop( Iop_And64,
+                               unop( Iop_Not64, mkexpr( cmp_mask ) ),
+                               mkU64( 0x0 ) ) ) );
+         assign( nan_cmp_value, mkU64( 0 ) );
+         break;
+      }
+
+   case 0x4C: //xscmpgedp
+      {
+         DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB);
+         /* compare src 1 >= src 2 */
+         /* result of Iop_CmpF64 is 0x40 if operands are equal,
+            mask is all 1's if equal. */
+         assign( cmp_mask,
+                 unop( Iop_1Sto64,
+                       unop(Iop_32to1,
+                            binop( Iop_Or32,
+                                   binop( Iop_Shr32,
+                                          binop(Iop_CmpF64,   /* EQ test */
+                                                unop( Iop_ReinterpI64asF64,
+                                                      mkexpr( src1 ) ),
+                                                unop( Iop_ReinterpI64asF64,
+                                                      mkexpr( src2 ) ) ),
+                                          mkU8( 6 ) ),
+                                   binop(Iop_CmpF64,  /* src2 < src 1 test */
+                                         unop( Iop_ReinterpI64asF64,
+                                               mkexpr( src2 ) ),
+                                         unop( Iop_ReinterpI64asF64,
+                                               mkexpr( src1 ) ) ) ) ) ) );
+         assign( word_result,
+                 binop( Iop_Or64,
+                        binop( Iop_And64, mkexpr( cmp_mask ),
+                               mkU64( 0xFFFFFFFFFFFFFFFF ) ),
+                        binop( Iop_And64,
+                               unop( Iop_Not64, mkexpr( cmp_mask ) ),
+                               mkU64( 0x0 ) ) ) );
+         assign( nan_cmp_value, mkU64( 0 ) );
+         break;
+      }
+
+   case 0x220: //xsmincdp
+      {
+         DIP("xsmincdp v%d,v%d,v%d\n", XT, XA, XB);
+         /* extract double-precision floating point source values from
+            double word 0 */
+
+         /* result of Iop_CmpF64 is 0x1 if src1 less then src2, */
+         assign( cmp_mask,
+                 unop( Iop_1Sto64,
+                       unop( Iop_32to1,
+                             binop(Iop_CmpF64,
+                                   unop( Iop_ReinterpI64asF64,
+                                         mkexpr( src1 ) ),
+                                   unop( Iop_ReinterpI64asF64,
+                                         mkexpr( src2 ) ) ) ) ) );
+         assign( word_result,
+                 binop( Iop_Or64,
+                        binop( Iop_And64, mkexpr( cmp_mask ), mkexpr( src1 ) ),
+                        binop( Iop_And64,
+                               unop( Iop_Not64, mkexpr( cmp_mask ) ),
+                               mkexpr( src2 ) ) ) );
+         assign( nan_cmp_value, mkexpr( src2 ) );
+         break;
+      }
+
+   default:
+      vex_printf( "dis_vx_misc(ppc)(opc2)\n" );
+      return False;
+   }
+
+   /* If either argument is NaN, result is src2.  If either argument is
+      SNaN, we are supposed to generate invalid operation exception.
+      Currently don't support generating exceptions.  In case of an
+      trap enabled invalid operation (SNaN) XT is not changed. The
+      snan_mask is setup appropriately for trap enabled or not.
+   */
+   assign( check_result,
+           binop( Iop_Or64,
+                  binop( Iop_And64, mkexpr( snan_mask ),
+                         unop( Iop_V128HIto64, mkexpr( xT ) ) ),
+                  binop( Iop_And64, unop( Iop_Not64,
+                                          mkexpr( snan_mask ) ),
+                         binop( Iop_Or64,
+                                binop( Iop_And64, mkexpr( nan_mask ),
+                                       mkexpr( nan_cmp_value ) ),
+                                binop( Iop_And64,
+                                       unop( Iop_Not64,
+                                             mkexpr( nan_mask ) ),
+                                       mkU64( 0 ) ) ) ) ) );
+
+   /* If SNaN is true, then the result is unchanged if a trap-enabled
+      Invalid Operation occurs.  Result mask already setup for trap-enabled
+      case.
+   */
+   putVSReg( XT,
+             binop( Iop_64HLtoV128,
+                    binop( Iop_Or64,
+                           binop( Iop_And64,
+                                  unop( Iop_Not64, mkexpr( result_mask ) ),
+                                  mkexpr( word_result ) ),
+                           binop( Iop_And64,
+                                  mkexpr( result_mask ),
+                                  mkexpr( check_result ) ) ),
+                    mkU64( 0 ) ) );
+   return True;
+}
+
 /*
  * VSX Logical Instructions
  */
@@ -27319,12 +27568,15 @@ static struct vsx_insn vsx_xx3[] = {
       { 0x0,  "xsaddsp" },
       { 0x4,  "xsmaddasp" },
       { 0x9,  "xsmaddmsp" },
+      { 0xC,  "xscmpeqdp" },
       { 0x20, "xssubsp" },
       { 0x24, "xsmaddmsp" },
+      { 0x2C, "xscmpgtdp" },
       { 0x3A, "xxpermr" },
       { 0x40, "xsmulsp" },
       { 0x44, "xsmsubasp" },
       { 0x48, "xxmrghw" },
+      { 0x4C, "xscmpgedp" },
       { 0x60, "xsdivsp" },
       { 0x64, "xsmsubmsp" },
       { 0x68, "xxperm" },
@@ -27371,6 +27623,7 @@ static struct vsx_insn vsx_xx3[] = {
       { 0x1f4, "xvtdivdp" },
       { 0x204, "xsnmaddasp" },
       { 0x208, "xxland" },
+      { 0x220, "xsmincdp" },
       { 0x224, "xsnmaddmsp" },
       { 0x228, "xxlandc" },
       { 0x244, "xsnmsubasp" },
@@ -28004,9 +28257,13 @@ DisResult disInstr_PPC_WRK (
             if (dis_vx_permute_misc(theInstr, vsxOpc2 ))
               goto decode_success;
             goto decode_failure;
+         case 0xC: case 0x2C: case 0x4C: // xscmpeqdp, xscmpgtdp, xscmpgedp
+         case 0x220: //xsmincdp
+            if (dis_vx_misc(theInstr, vsxOpc2)) goto decode_success;
+            goto decode_failure;
          case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor,
-         case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc
-         case 0x2C8: case 0x2E8: // xxlnand, xxleqv
+         case 0x208: case 0x228: // xxland, xxlandc
+         case 0x2A8: case 0x2C8: case 0x2E8: //  xxlorc, xxlnand, xxleqv
             if (dis_vx_logic(theInstr, vsxOpc2)) goto decode_success;
             goto decode_failure;
          case 0x0ec:             // xscmpexpdp

diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c
index 6e4e7dc39fcabfb64e2fb6489c88d0c3d804ed8a..4b07f8be754d7d1ac6bb633b24d3b1abf42412f3 100644 (file)
--- a/none/tests/ppc64/test_isa_3_0.c
+++ b/none/tests/ppc64/test_isa_3_0.c
@@ -1172,8 +1172,28 @@ static void test_xscmpexpdp(void) {
    };
 }
 
-static test_list_t testgroup_vector_scalar_compare_exp_double[] = {
+static void test_xscmpeqdp(void) {
+   __asm__ __volatile__ ("xscmpeqdp   %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
+}
+
+static void test_xscmpgtdp(void) {
+   __asm__ __volatile__ ("xscmpgtdp   %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
+}
+
+static void test_xscmpgedp(void) {
+   __asm__ __volatile__ ("xscmpgedp   %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
+}
+
+static void test_xsmincdp(void) {
+   __asm__ __volatile__ ("xsmincdp   %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
+}
+
+static test_list_t testgroup_vector_scalar_compare_double[] = {
    { &test_xscmpexpdp , "xscmpexpdp " },
+   { &test_xscmpeqdp , "xscmpeqdp " },
+   { &test_xscmpgtdp , "xscmpgtdp " },
+   { &test_xscmpgedp , "xscmpgedp " },
+   { &test_xsmincdp , "xsmincdp " },
    { NULL             , NULL          },
 };
 
@@ -2301,8 +2321,8 @@ static test_group_table_t all_tests[] = {
       PPC_MISC | PPC_TWO_ARGS,
    },
    {
-      testgroup_vector_scalar_compare_exp_double,
-      "ppc vector scalar compare exponents doubles",
+      testgroup_vector_scalar_compare_double,
+      "ppc vector scalar compare doubles",
       PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_COMPARE_ARGS,
    },
    {
@@ -3125,8 +3145,16 @@ static void testfunction_vector_scalar_two_quad (const char* instruction_name,
    }
 }
 
+/* helper macro.  Use below to limit output to only dword[0] for the inputs
+ * to the instructions listed here.  */
+#define instruction_only_uses_dword0_inputs(instruction_name) \
+       ((strncmp(instruction_name, "xscmpeqdp",9) == 0) || \
+        (strncmp(instruction_name, "xscmpgtdp",9) == 0) || \
+        (strncmp(instruction_name, "xscmpgedp",9) == 0) || \
+        (strncmp(instruction_name, "xsmincdp",8) == 0) )
+
 static void
-testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
+testfunction_vector_scalar_compare_double (const char* instruction_name,
                                                test_func_t test_function,
                                                unsigned int ignore_test_flags){
    int i,j;
@@ -3154,11 +3182,15 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
              */
             SET_CR_ZERO
             SET_FPSCR_ZERO
-
-            printf("%s %016lx %016lx %016lx %016lx",
-                   instruction_name,
-                   vec_xa[0], vec_xa[1],
-                   vec_xb[0], vec_xb[1]);
+            if (instruction_only_uses_dword0_inputs(instruction_name)) {
+               printf("%s %016lx %016lx",
+                      instruction_name, vec_xa[1], vec_xb[1]);
+            } else {
+               printf("%s %016lx %016lx %016lx %016lx",
+                      instruction_name,
+                      vec_xa[0], vec_xa[1],
+                      vec_xb[0], vec_xb[1]);
+            }
 
             if (verbose) printf(" cr#%d ", x_index);
 
@@ -3166,6 +3198,10 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
 
             (*test_function)();
 
+            if (instruction_only_uses_dword0_inputs(instruction_name)) {
+               printf("%016lx %016lx", vec_xt[0], vec_xt[1]);
+            }
+
             dissect_fpscr(local_fpscr);
             dissect_fpscr_result_value_class(local_fpscr);
             dissect_cr_rn(local_cr, x_index);
@@ -4094,7 +4130,7 @@ static void do_tests ( insn_sel_flags_t seln_flags)
                break;
 
             case PPC_COMPARE_ARGS:
-               group_function = &testfunction_vector_scalar_compare_exp_double;
+               group_function = &testfunction_vector_scalar_compare_double;
                break;
 
             default:

diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
index c4ad35f061db4644b2e5cfcce1cde337e1ae9472..7d3c94cb209a0b5ea75aac42f037408dbc4aa425 100644 (file)
--- a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
+++ b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
@@ -53311,8 +53311,8 @@ stxvb16x 00101f0000101f02 00101f0800101f10 [ 0001020304050607 5555555555555555 0
     00101f0800101f10 00101f0000101f02 [ 101f1000081f1000 021f1000001f1000 0000000000000000 ffffffffffffffff ]
 
 All done. Tested 135 different instructions
-ppc vector scalar compare exponents doubles:
-Test instruction group [ppc vector scalar compare exponents doubles]
+ppc vector scalar compare doubles:
+Test instruction group [ppc vector scalar compare doubles]
 xscmpexpdp  0000000000000000 0000000000000000 0000000000000000 0000000000000000 =>  FPCC-FE(EQ)
 xscmpexpdp  0000000000000000 0000000000000000 0000000000000000 00007fffffffffff =>  FPCC-FE(EQ)
 xscmpexpdp  0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff =>  FPCC-FE(EQ)
@@ -54275,7 +54275,3855 @@ xscmpexpdp  fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000
 xscmpexpdp  fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff =>  FPCC-FU(SO)
 xscmpexpdp  fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff =>  FPCC-FU(SO)
 
-All done. Tested 136 different instructions
+xscmpeqdp  0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp  0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
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+xsmincdp  fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 0000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 00007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 0ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 0ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp  fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+
+All done. Tested 140 different instructions
 ppc vector scalar test data class tests:
 Test instruction group [ppc vector scalar test data class tests]
 xststdcqp  0000000000000000, 0000000000000000 =>  0505050505050505, 0a0a0a0a0a0a0a0a
@@ -55453,7 +59301,7 @@ xvtstdcdp  0000000000000000, ffff7fffffffffff =>  0000000000000000, 000000000000
 xvtstdcdp  0000000000000000, ffff7fffffffffff =>  0000000000000000, 0000000000000000
 xvtstdcdp  0000000000000000, ffff7fffffffffff =>  0000000000000000, ffffffffffffffff
 
-All done. Tested 141 different instructions
+All done. Tested 145 different instructions
 ppc vector scalar tests against float double two args :
 Test instruction group [ppc vector scalar tests against float double two args ]
 xsiexpdp    r14 = 0x0, r15 = 0x0 0000000000000000 ffff7fffffffffff  =>  0000000000000000 0000000000000000
@@ -56261,4 +60109,4 @@ xvcvsphp    vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f800
 xvcvsphp    vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff  =>  0000000000000000 0000ffff0000ffff
 xvcvsphp    vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff  =>  0000000000000000 0000ffff0000ffff
 
-All done. Tested 146 different instructions
+All done. Tested 150 different instructions